先进应变硅CMOS器件饱和状态下载流子输运对随机掺杂诱导漏极电流变化的影响

E. Hsieh, S. Chung, C. Tsai, R. Huang, C. Tsai, C. Liang
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引用次数: 1

摘要

采用一种新的多元分析方法,对随机掺杂变化(RDF)引起的饱和漏极电流(Id,sat)的变化进行了广泛的研究。结果表明,流场Id、sat的变化来源于Vth、sat和饱和速度(Vsat),而Vth、sat的变化来源于漏阻降低(DIBL)。然而,实验结果表明,Vsat主导了Id,sat的变化。从输运理论出发,将Vsat进一步分解为Vinj和Bsat,表明Vinj是影响Id、sat变化的主导因素。Vinj速度越快,Id,sat的变化就越小。如果提高注入速度,则可以抑制Id,sat的变化。这是应变硅技术在CMOS器件缩放中的显著优势之一。
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The impact of the carrier transport on the random dopant induced drain current variation in the saturation regime of advanced strained-silicon CMOS devices
The variation of saturation drain current (Id,sat), induced by the random dopant variation (RDF), has been extensively studied by a new multivariate analysis method. It was found that the variation of Id,sat is originated from Vth,sat and saturation velocity (Vsat), while the variation of Vth,sat comes from the drain induced barrier lowering (DIBL). However, the experimental results shows that Vsat dominates the variation of Id,sat. From the transport theory, Vsat is further decomposed into Vinj and Bsat, showing that Vinj is the dominant factor of Id,sat variation. The faster the Vinj is, the less the Id,sat variation becomes. If one improves the injection velocity, then the variation of Id,sat can be suppressed. This has been one of the significant benefits of strained silicon technology in CMOS device scaling.
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