集成Cu和超低k介电(k=2.5/spl sim/2.2)，适用于65/45/32nm世代

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. Pub Date : 2005-12-05 DOI:10.1109/IEDM.2005.1609273

Y. Su, J. Shieh, J.S. Tsai, C. Ting, C.H. Lin, C. Chou, J.W. Hsu, S. Jang, M. Liang

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引用次数: 1

摘要

本文研究了将Cu和特低k介电介质(ELK, k=2.5~2.2)集成到双大马士革材料中的各种方法。我们展示了一种无灰工艺无k降解的沟槽优先硬掩膜工艺流程和一种新的孔隙密封技术。此外，我们已经将这种孔隙密封概念扩展到通过优先PR掩膜方法，用于多孔ELK为2.2。经过优化的硬掩膜和PR掩膜工艺流程都被证明有希望用于65/45/32nm代的Cu/ELK集成

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Integration of Cu and extra low-k dielectric (k=2.5/spl sim/2.2) for 65/45/32nm generations

This paper investigated various approaches to integrate Cu and extra low-k dielectric (ELK, k=2.5~2.2) for dual damascene fabrication. We demonstrate a trench-first hard mask process flow without k degradation by ash-free process and a novel pore sealing technique. In addition, we have extended this pore sealing concept to a via-first PR mask approach for porous ELK of 2.2. Both optimized hard mask and PR mask process flows are demonstrated promising for Cu/ELK integration for 65/45/32nm generations

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IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.

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