Brent Bohnenstiehl, Aaron Stillmaker, J. Pimentel, Timothy Andreas, Bin Liu, A. Tran, E. Adeagbo, B. Baas
{"title":"一个5.8 pJ/Op 1150亿ops/秒,到1.78万亿ops/秒的32nm千处理器阵列","authors":"Brent Bohnenstiehl, Aaron Stillmaker, J. Pimentel, Timothy Andreas, Bin Liu, A. Tran, E. Adeagbo, B. Baas","doi":"10.1109/VLSIC.2016.7573511","DOIUrl":null,"url":null,"abstract":"1000 programmable processors and 12 independent memory modules capable of simultaneously servicing both data and instruction requests are integrated onto a 32nm PD-SOI CMOS device. At 1.1 V, processors operate up to an average of 1.78 GHz yielding a maximum total chip computation rate of 1.78 trillion instructions/sec. At 0.84 V, 1000 cores execute 1 trillion instructions/sec while dissipating 13.1 W.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"47 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"45","resultStr":"{\"title\":\"A 5.8 pJ/Op 115 billion ops/sec, to 1.78 trillion ops/sec 32nm 1000-processor array\",\"authors\":\"Brent Bohnenstiehl, Aaron Stillmaker, J. Pimentel, Timothy Andreas, Bin Liu, A. Tran, E. Adeagbo, B. Baas\",\"doi\":\"10.1109/VLSIC.2016.7573511\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"1000 programmable processors and 12 independent memory modules capable of simultaneously servicing both data and instruction requests are integrated onto a 32nm PD-SOI CMOS device. At 1.1 V, processors operate up to an average of 1.78 GHz yielding a maximum total chip computation rate of 1.78 trillion instructions/sec. At 0.84 V, 1000 cores execute 1 trillion instructions/sec while dissipating 13.1 W.\",\"PeriodicalId\":6512,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"volume\":\"47 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"45\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2016.7573511\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2016.7573511","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 5.8 pJ/Op 115 billion ops/sec, to 1.78 trillion ops/sec 32nm 1000-processor array
1000 programmable processors and 12 independent memory modules capable of simultaneously servicing both data and instruction requests are integrated onto a 32nm PD-SOI CMOS device. At 1.1 V, processors operate up to an average of 1.78 GHz yielding a maximum total chip computation rate of 1.78 trillion instructions/sec. At 0.84 V, 1000 cores execute 1 trillion instructions/sec while dissipating 13.1 W.