{"title":"用于DRM/DAB/AM/FM频率合成器的高速宽带低相位噪声多模分频器","authors":"L. Xuemei, Wang Zhigong, Wang Keping","doi":"10.1109/EDSSC.2011.6117667","DOIUrl":null,"url":null,"abstract":"The implementation of a high-speed wide band low phase noise multi-mode frequency divider (MMFD) for a DRM/DAB frequency synthesizer is described. According to the characteristics of each part, novel SCL and CMOS static flip-flop DFF are applied. Realized in a 0.18-µm RF CMOS technology, the core area of the MMFD is 745 µm×705 µm, including buffer and pads. Post simulated results show that its operation frequency ranging is from 2.2GHz to 3.1 GHz, and phase noise of the MMFD is •134dBc/Hz at 10 kHz offset. The maximum core power consumption is 24.6 mA at a 1.8V power supply.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A high speed wide band low phase noise multi-mode frequency divider for DRM/DAB/AM/FM frequency synthesizer\",\"authors\":\"L. Xuemei, Wang Zhigong, Wang Keping\",\"doi\":\"10.1109/EDSSC.2011.6117667\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The implementation of a high-speed wide band low phase noise multi-mode frequency divider (MMFD) for a DRM/DAB frequency synthesizer is described. According to the characteristics of each part, novel SCL and CMOS static flip-flop DFF are applied. Realized in a 0.18-µm RF CMOS technology, the core area of the MMFD is 745 µm×705 µm, including buffer and pads. Post simulated results show that its operation frequency ranging is from 2.2GHz to 3.1 GHz, and phase noise of the MMFD is •134dBc/Hz at 10 kHz offset. The maximum core power consumption is 24.6 mA at a 1.8V power supply.\",\"PeriodicalId\":6363,\"journal\":{\"name\":\"2011 IEEE International Conference of Electron Devices and Solid-State Circuits\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-12-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE International Conference of Electron Devices and Solid-State Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDSSC.2011.6117667\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2011.6117667","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A high speed wide band low phase noise multi-mode frequency divider for DRM/DAB/AM/FM frequency synthesizer
The implementation of a high-speed wide band low phase noise multi-mode frequency divider (MMFD) for a DRM/DAB frequency synthesizer is described. According to the characteristics of each part, novel SCL and CMOS static flip-flop DFF are applied. Realized in a 0.18-µm RF CMOS technology, the core area of the MMFD is 745 µm×705 µm, including buffer and pads. Post simulated results show that its operation frequency ranging is from 2.2GHz to 3.1 GHz, and phase noise of the MMFD is •134dBc/Hz at 10 kHz offset. The maximum core power consumption is 24.6 mA at a 1.8V power supply.
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