高度可扩展的闪存,新颖的深沟槽隔离嵌入到高性能cmos中,用于90nm节点及以上

D. Shum, A. Tilke, L. Pescini, M. Stiftinger, R. Kakoschke, K.J. Han, S. Kim, V. Hecht, N. Chan, A. Yang, R. Broze
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引用次数: 8

摘要

一个具有90nm基本规则的闪存单元已嵌入到高性能(HP) CMOS逻辑工艺中。深沟隔离(DTi)工艺模块首次实现隔离Pwell (IPW)偏置方案,通过FN隧道实现闪存写入/擦除(W/E),而无需GIDL,这是低功耗(LP)电子产品的关键特性。IPW通过狭窄的井内和井间隔离空间实现了紧凑的单元设计和高度可扩展的高压(HV)外围。存储阵列由每个位线(BL)与相邻位线的DTi定义。高压偏置可以通过精心设计的逆行三井进行缩放,从而实现对称的门-井偏置
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Highly scalable flash memory with novel deep trench isolation embedded into highperformance cmos for the 90nm node & beyond
A flash memory cell with 90nm ground-rules has been embedded in a high performance (HP) CMOS logic process. A deep trench isolation (DTi) process module enables an isolated Pwell (IPW) bias scheme for the first time, leading to flash write/erase (W/E) by FN tunneling without GIDL, a key feature for low-power (LP) electronics. IPW leads to a compact cell design and a highly scalable high-voltage (HV) periphery through the narrow intrawell and interwell isolation spaces. The memory arrays are defined by DTi of each bitline (BL) from its neighboring BL. The HV bias can be scaled with a carefully designed retrograde triple-well that enables a symmetrical gate-well bias
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