D. Shum, A. Tilke, L. Pescini, M. Stiftinger, R. Kakoschke, K.J. Han, S. Kim, V. Hecht, N. Chan, A. Yang, R. Broze
{"title":"高度可扩展的闪存,新颖的深沟槽隔离嵌入到高性能cmos中,用于90nm节点及以上","authors":"D. Shum, A. Tilke, L. Pescini, M. Stiftinger, R. Kakoschke, K.J. Han, S. Kim, V. Hecht, N. Chan, A. Yang, R. Broze","doi":"10.1109/IEDM.2005.1609346","DOIUrl":null,"url":null,"abstract":"A flash memory cell with 90nm ground-rules has been embedded in a high performance (HP) CMOS logic process. A deep trench isolation (DTi) process module enables an isolated Pwell (IPW) bias scheme for the first time, leading to flash write/erase (W/E) by FN tunneling without GIDL, a key feature for low-power (LP) electronics. IPW leads to a compact cell design and a highly scalable high-voltage (HV) periphery through the narrow intrawell and interwell isolation spaces. The memory arrays are defined by DTi of each bitline (BL) from its neighboring BL. The HV bias can be scaled with a carefully designed retrograde triple-well that enables a symmetrical gate-well bias","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"9 1","pages":"344-347"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Highly scalable flash memory with novel deep trench isolation embedded into highperformance cmos for the 90nm node & beyond\",\"authors\":\"D. Shum, A. Tilke, L. Pescini, M. Stiftinger, R. Kakoschke, K.J. Han, S. Kim, V. Hecht, N. Chan, A. Yang, R. Broze\",\"doi\":\"10.1109/IEDM.2005.1609346\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A flash memory cell with 90nm ground-rules has been embedded in a high performance (HP) CMOS logic process. A deep trench isolation (DTi) process module enables an isolated Pwell (IPW) bias scheme for the first time, leading to flash write/erase (W/E) by FN tunneling without GIDL, a key feature for low-power (LP) electronics. IPW leads to a compact cell design and a highly scalable high-voltage (HV) periphery through the narrow intrawell and interwell isolation spaces. The memory arrays are defined by DTi of each bitline (BL) from its neighboring BL. The HV bias can be scaled with a carefully designed retrograde triple-well that enables a symmetrical gate-well bias\",\"PeriodicalId\":13071,\"journal\":{\"name\":\"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.\",\"volume\":\"9 1\",\"pages\":\"344-347\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2005.1609346\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2005.1609346","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Highly scalable flash memory with novel deep trench isolation embedded into highperformance cmos for the 90nm node & beyond
A flash memory cell with 90nm ground-rules has been embedded in a high performance (HP) CMOS logic process. A deep trench isolation (DTi) process module enables an isolated Pwell (IPW) bias scheme for the first time, leading to flash write/erase (W/E) by FN tunneling without GIDL, a key feature for low-power (LP) electronics. IPW leads to a compact cell design and a highly scalable high-voltage (HV) periphery through the narrow intrawell and interwell isolation spaces. The memory arrays are defined by DTi of each bitline (BL) from its neighboring BL. The HV bias can be scaled with a carefully designed retrograde triple-well that enables a symmetrical gate-well bias