{"title":"HCD在HKMG FDSOI mosfet中工艺和偏置依赖性的SPICE兼容紧凑模型","authors":"Uma Sharma, S. Mahapatra","doi":"10.1109/sispad.2019.8870457","DOIUrl":null,"url":null,"abstract":"A SPICE compatible model is developed for the time kinetics of linear drain current drift (ΔI<inf>DLIN</inf>) under Hot Carrier Degradation (HCD) stress in 28 nm Fully Depleted Silicon On Insulator (FDSOI) n-channel FETs having High-K Metal Gate (HKMG) gate stack. The impact of varying the drain (V<inf>D</inf>), gate (V<inf>G</inf>) and body (V<inf>BB</inf>) biases is modeled. The framework is also capable of modeling the channel length (L<inf>CH</inf>) and gate-oxide thickness (T<inf>OX</inf>) variations. Impact of Self-Heating Effect (SHE) has also been taken into consideration during ΔI<inf>DLIN</inf> modeling.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A SPICE Compatible Compact Model for Process and Bias Dependence of HCD in HKMG FDSOI MOSFETs\",\"authors\":\"Uma Sharma, S. Mahapatra\",\"doi\":\"10.1109/sispad.2019.8870457\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A SPICE compatible model is developed for the time kinetics of linear drain current drift (ΔI<inf>DLIN</inf>) under Hot Carrier Degradation (HCD) stress in 28 nm Fully Depleted Silicon On Insulator (FDSOI) n-channel FETs having High-K Metal Gate (HKMG) gate stack. The impact of varying the drain (V<inf>D</inf>), gate (V<inf>G</inf>) and body (V<inf>BB</inf>) biases is modeled. The framework is also capable of modeling the channel length (L<inf>CH</inf>) and gate-oxide thickness (T<inf>OX</inf>) variations. Impact of Self-Heating Effect (SHE) has also been taken into consideration during ΔI<inf>DLIN</inf> modeling.\",\"PeriodicalId\":6755,\"journal\":{\"name\":\"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)\",\"volume\":\"1 1\",\"pages\":\"1-4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/sispad.2019.8870457\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/sispad.2019.8870457","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A SPICE Compatible Compact Model for Process and Bias Dependence of HCD in HKMG FDSOI MOSFETs
A SPICE compatible model is developed for the time kinetics of linear drain current drift (ΔIDLIN) under Hot Carrier Degradation (HCD) stress in 28 nm Fully Depleted Silicon On Insulator (FDSOI) n-channel FETs having High-K Metal Gate (HKMG) gate stack. The impact of varying the drain (VD), gate (VG) and body (VBB) biases is modeled. The framework is also capable of modeling the channel length (LCH) and gate-oxide thickness (TOX) variations. Impact of Self-Heating Effect (SHE) has also been taken into consideration during ΔIDLIN modeling.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
