22FDX®平台及其他平台的射频性能改进

T. Herrmann, A. Zaka, N. Subramani, Zhixing Zhao, S. Lehmann, Y. Andee
{"title":"22FDX®平台及其他平台的射频性能改进","authors":"T. Herrmann, A. Zaka, N. Subramani, Zhixing Zhao, S. Lehmann, Y. Andee","doi":"10.1109/SISPAD.2019.8870435","DOIUrl":null,"url":null,"abstract":"The paper describes manufacturing process and layout optimizations to improve RF performance of 22FDX® N/PFET devices, based on a comprehensive calibration of DC and RF figures of merit. Process and Device simulations of the individual and combined elements show ft/fmax improvement up to about 1.13/1.1x (NFET) and about 1.32/1.24x (PFET) over standard devices mainly driven by mechanical stress and parasitic R/C elements.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"9 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"RF performance improvement on 22FDX® platform and beyond\",\"authors\":\"T. Herrmann, A. Zaka, N. Subramani, Zhixing Zhao, S. Lehmann, Y. Andee\",\"doi\":\"10.1109/SISPAD.2019.8870435\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper describes manufacturing process and layout optimizations to improve RF performance of 22FDX® N/PFET devices, based on a comprehensive calibration of DC and RF figures of merit. Process and Device simulations of the individual and combined elements show ft/fmax improvement up to about 1.13/1.1x (NFET) and about 1.32/1.24x (PFET) over standard devices mainly driven by mechanical stress and parasitic R/C elements.\",\"PeriodicalId\":6755,\"journal\":{\"name\":\"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)\",\"volume\":\"9 1\",\"pages\":\"1-4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SISPAD.2019.8870435\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SISPAD.2019.8870435","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

本文介绍了制造工艺和布局优化,以提高22FDX®N/ fet器件的射频性能,基于直流和射频性能的综合校准。单个元件和组合元件的工艺和器件模拟显示,与主要由机械应力和寄生R/C元件驱动的标准器件相比,ft/fmax提高了约1.13/1.1倍(fet)和约1.32/1.24倍(fet)。
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RF performance improvement on 22FDX® platform and beyond
The paper describes manufacturing process and layout optimizations to improve RF performance of 22FDX® N/PFET devices, based on a comprehensive calibration of DC and RF figures of merit. Process and Device simulations of the individual and combined elements show ft/fmax improvement up to about 1.13/1.1x (NFET) and about 1.32/1.24x (PFET) over standard devices mainly driven by mechanical stress and parasitic R/C elements.
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