嵌入式高k电荷阱多时间可编程存储器，可扩展至14nm FIN，无需增加工艺复杂性

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI:10.1109/VLSIC.2016.7573462

Janakiraman Viraraghavan, D. Leu, Balaji Jayaraman, A. Cestero, Robert Kilker, M. Yin, J. Golz, R. R. Tummuru, Ramesh Raghavan, D. Moy, Thejas Kempanna, F. Khan, T. Kirihata, S. Iyer

{"title":"嵌入式高k电荷阱多时间可编程存储器，可扩展至14nm FIN，无需增加工艺复杂性","authors":"Janakiraman Viraraghavan, D. Leu, Balaji Jayaraman, A. Cestero, Robert Kilker, M. Yin, J. Golz, R. R. Tummuru, Ramesh Raghavan, D. Moy, Thejas Kempanna, F. Khan, T. Kirihata, S. Iyer","doi":"10.1109/VLSIC.2016.7573462","DOIUrl":null,"url":null,"abstract":"An 80Kb logic Embedded Multi-Time Programmable Memory (MTPM) employs charge trapping and de-trapping behavior in 32nm/22nm High-K transistor, resulting in no added process complexity. Multi-step verification with overwrite protection employs block-write and signal margin degradation (~30%) to satisfy 10 year retention at 105° C.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"1998 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity\",\"authors\":\"Janakiraman Viraraghavan, D. Leu, Balaji Jayaraman, A. Cestero, Robert Kilker, M. Yin, J. Golz, R. R. Tummuru, Ramesh Raghavan, D. Moy, Thejas Kempanna, F. Khan, T. Kirihata, S. Iyer\",\"doi\":\"10.1109/VLSIC.2016.7573462\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An 80Kb logic Embedded Multi-Time Programmable Memory (MTPM) employs charge trapping and de-trapping behavior in 32nm/22nm High-K transistor, resulting in no added process complexity. Multi-step verification with overwrite protection employs block-write and signal margin degradation (~30%) to satisfy 10 year retention at 105° C.\",\"PeriodicalId\":6512,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"volume\":\"1998 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2016.7573462\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2016.7573462","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 11

摘要

80Kb逻辑嵌入式多时间可编程存储器(MTPM)在32nm/22nm高k晶体管中采用电荷捕获和释放行为，不会增加工艺复杂性。具有覆盖保护的多步验证采用块写入和信号裕度退化(~30%)，以满足105°C下10年的保留。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity

An 80Kb logic Embedded Multi-Time Programmable Memory (MTPM) employs charge trapping and de-trapping behavior in 32nm/22nm High-K transistor, resulting in no added process complexity. Multi-step verification with overwrite protection employs block-write and signal margin degradation (~30%) to satisfy 10 year retention at 105° C.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)

自引率

0.00%

发文量