A 1.6 ns access, 1 GHz two-way set-predicted and sum-indexed 64-kByte data cache

A 64-kByte cache exploits combined address generation and word line decoding in the SRAM array, translation array, and directory. In place of a late select, set selection in the two-way associative cache is accomplished in the decode path by accessing a stored prediction from a sum-indexed array built into the decoder.