紧凑型446 Gbps/W AES加速器，适用于40nm的移动SoC和物联网

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI:10.1109/VLSIC.2016.7573553

Yiqun Zhang, Kaiyuan Yang, Mehdi Saligane, D. Blaauw, D. Sylvester

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引用次数: 34

摘要

针对节能、低成本移动和物联网应用的AES硬件加速器采用40nm CMOS制造。提出的设计消除了传统AES实现中的ShiftRow级，并使用重新定时的锁存器取代了数据和密钥存储中的触发器，节省了25%的面积和69%的功耗。加上原生GF(24)2复合场计算和故障减少技术中的2级Sbox，这使得紧凑的2228栅极设计在0.47V下实现了446 Gbps/W和46.2 Mbps的吞吐量。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A compact 446 Gbps/W AES accelerator for mobile SoC and IoT in 40nm

An AES hardware accelerator targeting energy efficient, low cost mobile and IoT applications is fabricated in 40nm CMOS. The proposed design eliminates the ShiftRow stage in conventional AES implementations and replaces flip-flops in data and key storage with latches using re-timing, saving 25% area and 69% power. Along with a 2-stage Sbox in native GF(24)2 composite-field computation and glitch reduction techniques, this results in a compact 2228 gate design achieving 446 Gbps/W and 46.2 Mbps throughput at 0.47V.

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2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)

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