Design of a low-power adaptive LMS equalizer for hearing-aid applications

This paper presents the design process and partial results of a low-power adaptive least mean squares (LMS) equalizer for hearing-aid applications. Energy efficiency is achieved by using a fully-serial (FS) architecture working in the above-threshold region. Prototype chips have been sent to manufacture in a standard CMOS 0.18 μm process. Partial results, comparing the behavioral and functional models, have shown a maximum error of 2.54% for the same inputs and channel characteristics. By choosing an architecture in which the priority is energy consumption rather than speed, it was possible to achieve about 140 nJ energy dissipation per sample.