位错应力场模型及其应用研究进展

U. Kwon, Jeong-Guk Min, Seon-Young Lee, Alexander Schmidt, D. Kim, Yasuyuki Kayama, Yutaka Nishizawa, Kiyoshi Ishikawa
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引用次数: 1

摘要

位错产生的应力场的TCAD预测对下一代逻辑器件的应力源优化至关重要。本文提出了一种新的位错应力场计算方法及其在应变硅器件中的应用。该方法将位错岩心的解析应力场模型与连续有限元应力求解相结合,得到力学平衡。将其应用于位错应力记忆技术(D-SMT)的设计优化、其局部布局效应(LLE)建模以及Si/SiGe界面点阵失配应变的松弛,从而降低eSiGe应力。仿真结果与实验结果进行了验证。
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Progress in dislocation stress field model and its appications
TCAD prediction of the stress field generated by dislocation is crucial for the optimization of stressors for next generation logic devices. In this paper, we present a new hybrid approach for dislocation stress field calculation and its application to strained Si devices. New methodology combines an analytic stress field model for dislocation cores and consecutive FEM stress solving to get mechanical equilibrium. It was applied to the design optimization of dislocation stress memorization technique (D-SMT), its local layout effect (LLE) modeling, and the relaxation of lattice mismatch strain at Si/SiGe interface which degrades eSiGe stress. All the simulation results were verified with experimental results.
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