一个8.2 mw 10-b 1.6-GS/s 4× TI SAR ADC，具有快速参考电荷中和和16nm CMOS背景时偏校准功能

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI:10.1109/VLSIC.2016.7573536

Ying-Zu Lin, Chih-Hou Tsai, Shan-Chih Tsou, Chao-Hsin Lu

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引用次数: 28

摘要

提出了一种具有快速基准电荷中和和背景时偏校准功能的4路1.6 gs /s时交错SAR ADC。SAR子adc采用无触发器数字控制单元实现400MS/s的操作。16纳米CMOS的原型占据0.023 mm2的有效面积。在0.95 v的电源下，1.6 GS/s的功耗为8.2 mW。峰值SNDR为55 dB，高频FOM为19 fJ/转换步长。

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A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS

This paper presents a 4-way 1.6-GS/s time-interleaved (TI) SAR ADC with fast reference charge neutralization (CN) and background timing-skew calibration. The SAR sub-ADC uses a flip-flop-less digital control unit to achieve 400MS/s operation. The prototype in 16-nm CMOS occupies an active area of 0.023 mm2. From a 0.95-V supply, the power consumption is 8.2 mW at 1.6 GS/s. The peak SNDR is 55 dB and HF FOM is 19 fJ/conversion-step.

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2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)

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