470ps 64位并行二进制加法器[用于CPU芯片]

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) Pub Date : 2000-06-15 DOI:10.1109/VLSIC.2000.852887

Jaehong Park, H. Ngo, S. Dhong

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引用次数: 30

摘要

本文提出了一种在1 GHz研究原型64位PowerPC微处理器上实现的快速64位并行进位预判二进制加法器。动态复合门的有效使用使加法器在延迟复位动态逻辑的三个阶段实现。计算只使用G(生成)和P(传播)，并且从G、P和频闪信号计算进位的逆。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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470 ps 64-bit parallel binary adder [for CPU chip]

This paper presents a fast 64-bit parallel carry look-ahead binary adder implemented in a 1 GHz research prototype 64-bit PowerPC microprocessor. Efficient use of dynamic compound gates enables implementation of the adder in just three stages of delayed reset dynamic logic. The computation uses only G (Generate) and P (Propagate), and the inverse of Carry is computed from G, P, and a strobe signal.

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2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)

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