一种新颖的双端口6T CMOS SRAM单元结构,用于具有单比特线同时读写访问(SBLSRWA)能力的低压VLSI SRAM

Bo-Ting Wang, J. B. Kuo
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引用次数: 8

摘要

本文报道了一种双端口6T CMOS SRAM单元结构,用于具有单比特线同时读写访问(SBLSRWA)能力的低压VLSI SRAM。SRAM单元具有独特的结构,将NMOS器件的源端连接到写字线,该SRAM单元可用于为1V双端口VLSI SRAM提供SBLSRWA能力,并经SPICE结果验证。
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A novel two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability
This paper reports a two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability. With a unique structure connecting the source terminal of an NMOS device in the SRAM cell to the write word line, this SRAM cell can be used to provide SBLSRWA capability for 1V two-port VLSI SRAM as verified by SPICE results.
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A novel class A CMOS current conveyor Adaptive envelope-constrained filter design Phenomenological model of false lock in the sampling phase-locked loop A novel two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability Real-time calculus for scheduling hard real-time systems
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