从器件到电路:模拟5nm纳米片的性能

2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) Pub Date : 2019-09-01 DOI:10.1109/SISPAD.2019.8870357

A. Brown, Liping Wang, P. Asenov, F. Klüpfel, B. Cheng, S. Martinie, O. Rozeau, S. Barraud, J. Barbe, C. Millar, J. Lorenz

{"title":"从器件到电路:模拟5nm纳米片的性能","authors":"A. Brown, Liping Wang, P. Asenov, F. Klüpfel, B. Cheng, S. Martinie, O. Rozeau, S. Barraud, J. Barbe, C. Millar, J. Lorenz","doi":"10.1109/SISPAD.2019.8870357","DOIUrl":null,"url":null,"abstract":"A simulation flow for design-technology co-optimisation using 5nm stacked nanowires is presented. The effect of variation in key process parameters on the behaviour of benchmark circuits is examined through the use of variability-aware compact models, accounting for both global and local variability.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"15 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"From devices to circuits: modelling the performance of 5nm nanosheets\",\"authors\":\"A. Brown, Liping Wang, P. Asenov, F. Klüpfel, B. Cheng, S. Martinie, O. Rozeau, S. Barraud, J. Barbe, C. Millar, J. Lorenz\",\"doi\":\"10.1109/SISPAD.2019.8870357\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A simulation flow for design-technology co-optimisation using 5nm stacked nanowires is presented. The effect of variation in key process parameters on the behaviour of benchmark circuits is examined through the use of variability-aware compact models, accounting for both global and local variability.\",\"PeriodicalId\":6755,\"journal\":{\"name\":\"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)\",\"volume\":\"15 1\",\"pages\":\"1-4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SISPAD.2019.8870357\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SISPAD.2019.8870357","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

提出了一种利用5nm堆叠纳米线进行设计-技术协同优化的仿真流程。关键过程参数变化对基准电路行为的影响通过使用可变感知紧凑模型进行检查，考虑全局和局部可变性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

From devices to circuits: modelling the performance of 5nm nanosheets

A simulation flow for design-technology co-optimisation using 5nm stacked nanowires is presented. The effect of variation in key process parameters on the behaviour of benchmark circuits is examined through the use of variability-aware compact models, accounting for both global and local variability.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

自引率

0.00%

发文量