28nm CMOS 180 mW多标准电视调谐器

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI:10.1109/VLSIC.2016.7573502

Jianhong Xiao, Weinan Gao, Xiaojing Xu, D. Chang, Jiang Cao, R. Sun, Vijayaramalingam Periasamy, N. Wang, Xi Chen, G. Unruh, Takayuki Hayashi, T. Chih, L. Krishnan, Kuo-Ken Huang, Sunny Raj Dommaraju, Guowen Wei, B. Shen, Ardie G. Venes, D. Koh, J. Chang

{"title":"28nm CMOS 180 mW多标准电视调谐器","authors":"Jianhong Xiao, Weinan Gao, Xiaojing Xu, D. Chang, Jiang Cao, R. Sun, Vijayaramalingam Periasamy, N. Wang, Xi Chen, G. Unruh, Takayuki Hayashi, T. Chih, L. Krishnan, Kuo-Ken Huang, Sunny Raj Dommaraju, Guowen Wei, B. Shen, Ardie G. Venes, D. Koh, J. Chang","doi":"10.1109/VLSIC.2016.7573502","DOIUrl":null,"url":null,"abstract":"A 28 nm CMOS multistandard TV tuner is presented. A power-efficient RF front end and >80 dB dynamic range ΔΣ ADC, together with a smart AGC algorithm, enable this tuner to achieve 64 dB ATSC A/74 N+6 ACI while dissipating only 180 mW. A baseband resistor weighting harmonic rejection mixer clocked by a 7-13.6 GHz PLL and single-edge-triggered shift registers achieves >58 dB harmonic rejection ratio at frequencies up to 827 MHz.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"29 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 180 mW multistandard TV tuner in 28 nm CMOS\",\"authors\":\"Jianhong Xiao, Weinan Gao, Xiaojing Xu, D. Chang, Jiang Cao, R. Sun, Vijayaramalingam Periasamy, N. Wang, Xi Chen, G. Unruh, Takayuki Hayashi, T. Chih, L. Krishnan, Kuo-Ken Huang, Sunny Raj Dommaraju, Guowen Wei, B. Shen, Ardie G. Venes, D. Koh, J. Chang\",\"doi\":\"10.1109/VLSIC.2016.7573502\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 28 nm CMOS multistandard TV tuner is presented. A power-efficient RF front end and >80 dB dynamic range ΔΣ ADC, together with a smart AGC algorithm, enable this tuner to achieve 64 dB ATSC A/74 N+6 ACI while dissipating only 180 mW. A baseband resistor weighting harmonic rejection mixer clocked by a 7-13.6 GHz PLL and single-edge-triggered shift registers achieves >58 dB harmonic rejection ratio at frequencies up to 827 MHz.\",\"PeriodicalId\":6512,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"volume\":\"29 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2016.7573502\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2016.7573502","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

介绍了一种28纳米CMOS多标准电视调谐器。低功耗RF前端和>80 dB动态范围ΔΣ ADC，加上智能AGC算法，使该调谐器能够实现64 dB ATSC A/74 N+6 ACI，同时功耗仅为180 mW。由7-13.6 GHz锁相环和单边触发移位寄存器时钟的基带电阻加权谐波抑制混频器在高达827 MHz的频率下实现>58 dB的谐波抑制比。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

A 180 mW multistandard TV tuner in 28 nm CMOS

A 28 nm CMOS multistandard TV tuner is presented. A power-efficient RF front end and >80 dB dynamic range ΔΣ ADC, together with a smart AGC algorithm, enable this tuner to achieve 64 dB ATSC A/74 N+6 ACI while dissipating only 180 mW. A baseband resistor weighting harmonic rejection mixer clocked by a 7-13.6 GHz PLL and single-edge-triggered shift registers achieves >58 dB harmonic rejection ratio at frequencies up to 827 MHz.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)

自引率

0.00%

发文量