{"title":"一种用于尖峰神经网络的低功耗、低面积混合信号神经元细胞","authors":"Carolina Raymond, Eric Gutierrez","doi":"10.1109/MWSCAS47672.2021.9531863","DOIUrl":null,"url":null,"abstract":"We propose a simple neuronal cell for the implementation of low power and low area spiking neural networks. The neuronal cell mimics the performance of biological neural systems by combining both analog and digital circuits. This mixed-signal approach makes use of minimum-size sub-threshold biased devices. Additionally, conventional leaky integrate-and-fire model is simplified leading to smaller and simpler neuronal cells. The proposed cell is designed using a 50-nm CMOS node and its performance is validated by transient simulation. Power consumption and area are estimated, showing great potential in comparison to equivalent state-of-the-art solutions. Finally behavioral equations are proposed and matched to transient schematic simulations to make them available for future training tasks. The proposed neuronal cell attempts to become a suitable solution for ultra-low power smart devices with computing at the edge, such as wearables or remote sensors.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"64 1","pages":"313-316"},"PeriodicalIF":0.0000,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A low power and low area mixed-signal neuronal cell for spiking neural networks\",\"authors\":\"Carolina Raymond, Eric Gutierrez\",\"doi\":\"10.1109/MWSCAS47672.2021.9531863\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose a simple neuronal cell for the implementation of low power and low area spiking neural networks. The neuronal cell mimics the performance of biological neural systems by combining both analog and digital circuits. This mixed-signal approach makes use of minimum-size sub-threshold biased devices. Additionally, conventional leaky integrate-and-fire model is simplified leading to smaller and simpler neuronal cells. The proposed cell is designed using a 50-nm CMOS node and its performance is validated by transient simulation. Power consumption and area are estimated, showing great potential in comparison to equivalent state-of-the-art solutions. Finally behavioral equations are proposed and matched to transient schematic simulations to make them available for future training tasks. The proposed neuronal cell attempts to become a suitable solution for ultra-low power smart devices with computing at the edge, such as wearables or remote sensors.\",\"PeriodicalId\":6792,\"journal\":{\"name\":\"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)\",\"volume\":\"64 1\",\"pages\":\"313-316\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-08-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS47672.2021.9531863\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS47672.2021.9531863","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A low power and low area mixed-signal neuronal cell for spiking neural networks
We propose a simple neuronal cell for the implementation of low power and low area spiking neural networks. The neuronal cell mimics the performance of biological neural systems by combining both analog and digital circuits. This mixed-signal approach makes use of minimum-size sub-threshold biased devices. Additionally, conventional leaky integrate-and-fire model is simplified leading to smaller and simpler neuronal cells. The proposed cell is designed using a 50-nm CMOS node and its performance is validated by transient simulation. Power consumption and area are estimated, showing great potential in comparison to equivalent state-of-the-art solutions. Finally behavioral equations are proposed and matched to transient schematic simulations to make them available for future training tasks. The proposed neuronal cell attempts to become a suitable solution for ultra-low power smart devices with computing at the edge, such as wearables or remote sensors.