M. Muller, A. Mondot, N. Gierczynski, D. Aimé, B. Froment, F. Leverd, P. Gouraud, A. Talbot, S. Descombes, Y. Morand, Y. Le Tiec, P. Besson, A. Toffoli, G. Ribes, J. Roux, S. Pokrant, F. Andre, T. Skotnicki
{"title":"一种易于集成的NiSi tosi门/ sion模块,用于LP SRAM应用,基于门和结的单步硅化","authors":"M. Muller, A. Mondot, N. Gierczynski, D. Aimé, B. Froment, F. Leverd, P. Gouraud, A. Talbot, S. Descombes, Y. Morand, Y. Le Tiec, P. Besson, A. Toffoli, G. Ribes, J. Roux, S. Pokrant, F. Andre, T. Skotnicki","doi":"10.1109/IEDM.2005.1609428","DOIUrl":null,"url":null,"abstract":"In this paper, we present a CMOS NiSi totally silicided (TOSI)-gate on SiON module, based on a single step silicidation of the junctions and the total gate, and demonstrate its industrial feasibility on SRAM demonstrators. The single step silicidation is achieved by the use of an ultra-low initial Si gate electrode and selective S/D epitaxy, which allows us to avoid any additional CMP step. We show excellent transistor morphology, good device results and first functional NiSi TOSI-gate SRAMs in a state-of-the-art industrial cell size indicating the potential of our TOSI integration module for LP applications","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"281 2 1","pages":"626-629"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"An easily integrable NiSi TOSI-gate/SiON-module for LP SRAM applications based on a single step silicidation of gate and junction\",\"authors\":\"M. Muller, A. Mondot, N. Gierczynski, D. Aimé, B. Froment, F. Leverd, P. Gouraud, A. Talbot, S. Descombes, Y. Morand, Y. Le Tiec, P. Besson, A. Toffoli, G. Ribes, J. Roux, S. Pokrant, F. Andre, T. Skotnicki\",\"doi\":\"10.1109/IEDM.2005.1609428\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we present a CMOS NiSi totally silicided (TOSI)-gate on SiON module, based on a single step silicidation of the junctions and the total gate, and demonstrate its industrial feasibility on SRAM demonstrators. The single step silicidation is achieved by the use of an ultra-low initial Si gate electrode and selective S/D epitaxy, which allows us to avoid any additional CMP step. We show excellent transistor morphology, good device results and first functional NiSi TOSI-gate SRAMs in a state-of-the-art industrial cell size indicating the potential of our TOSI integration module for LP applications\",\"PeriodicalId\":13071,\"journal\":{\"name\":\"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.\",\"volume\":\"281 2 1\",\"pages\":\"626-629\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2005.1609428\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2005.1609428","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An easily integrable NiSi TOSI-gate/SiON-module for LP SRAM applications based on a single step silicidation of gate and junction
In this paper, we present a CMOS NiSi totally silicided (TOSI)-gate on SiON module, based on a single step silicidation of the junctions and the total gate, and demonstrate its industrial feasibility on SRAM demonstrators. The single step silicidation is achieved by the use of an ultra-low initial Si gate electrode and selective S/D epitaxy, which allows us to avoid any additional CMP step. We show excellent transistor morphology, good device results and first functional NiSi TOSI-gate SRAMs in a state-of-the-art industrial cell size indicating the potential of our TOSI integration module for LP applications