Design of CNFET-based Low-Power Ternary Sequential Logic circuits

Scaling of transistors beyond a certain limit is giving rise to problems in the traditional CMOS (Complementary - Metal-Oxide-Semiconductor) technology. This has lead researchers to explore newer technologies like the CNFET(Carbon-Nanotube-Field-Effect- Transistor). Design of ternary logic circuits using CNFETs has been gaining interest recently which gives benefits for power consumption, interconnection etc when compared to binary logic. Various ternary sequential circuits have been implemented in literature. This paper proposes a new designs for sequential circuits like D-latch and D-flipflop. The proposed successor-predecessor based latch design is multiplexer based that optimises power consumption when compared to existing designs. Ternary flipflop is also designed using the proposed mux based latch design. All the proposed designs are simulated using HSPICE and a standard Stanford CNFET model. Simulation results for the proposed successor-predecessor based D-latch design and proposed D-flipflop design shows an improvement of upto 36% and 51% in power respectively, as compared to designs existing in literature.