{"title":"一种新型低功率高数据速率BPSK解调器","authors":"B. Wang, H. Liu, M. Zhao, B. Li","doi":"10.1109/EDSSC.2011.6117625","DOIUrl":null,"url":null,"abstract":"A novel binary phase-shift keying (BPSK) demodulator architecture is presented. The design is fully digital and based on trigger receiving. The demodulator can be applied in wireless communications, biological implants, portable facilities because of its low complexity, low power and high data rate. The prototype chip is fabricated in a 0.35-µm CMOS process and the area of the designed circuits is about 0.5 mm2. Measurement results reveal that the designed demodulator consumes only 319 µw power for the data rate of 10.7MHz 1M bit/s, results also show that it can work well to the high data rate of 100MHz 10M bit/s, which is the highest performance of the BPSK demodulator.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"30 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A novel low-power high-date-rate BPSK demodulator\",\"authors\":\"B. Wang, H. Liu, M. Zhao, B. Li\",\"doi\":\"10.1109/EDSSC.2011.6117625\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel binary phase-shift keying (BPSK) demodulator architecture is presented. The design is fully digital and based on trigger receiving. The demodulator can be applied in wireless communications, biological implants, portable facilities because of its low complexity, low power and high data rate. The prototype chip is fabricated in a 0.35-µm CMOS process and the area of the designed circuits is about 0.5 mm2. Measurement results reveal that the designed demodulator consumes only 319 µw power for the data rate of 10.7MHz 1M bit/s, results also show that it can work well to the high data rate of 100MHz 10M bit/s, which is the highest performance of the BPSK demodulator.\",\"PeriodicalId\":6363,\"journal\":{\"name\":\"2011 IEEE International Conference of Electron Devices and Solid-State Circuits\",\"volume\":\"30 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-12-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE International Conference of Electron Devices and Solid-State Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDSSC.2011.6117625\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2011.6117625","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel binary phase-shift keying (BPSK) demodulator architecture is presented. The design is fully digital and based on trigger receiving. The demodulator can be applied in wireless communications, biological implants, portable facilities because of its low complexity, low power and high data rate. The prototype chip is fabricated in a 0.35-µm CMOS process and the area of the designed circuits is about 0.5 mm2. Measurement results reveal that the designed demodulator consumes only 319 µw power for the data rate of 10.7MHz 1M bit/s, results also show that it can work well to the high data rate of 100MHz 10M bit/s, which is the highest performance of the BPSK demodulator.
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