{"title":"混合定向finFET CMOS技术的双应力封盖层增强研究","authors":"K. Shin, C. O. Chui, T. King","doi":"10.1109/IEDM.2005.1609528","DOIUrl":null,"url":null,"abstract":"3D stress in FinFET and tri-gate FET structures induced by a tensile or compressive capping layer is studied via simulation. The classic bulk-Si piezoresistance model is then used to predict the impact on carrier mobilities. A tensile capping layer is expected to provide dramatic enhancements (>100%) in electron mobility for a (100)-sidewall fin with lang100rang current flow, while a compressive capping layer is expected to provide modest enhancement (<25%) in hole mobility for a (110)-sidewall fin with lang110rang current flow. Mobility enhancement will be greater for fins with higher aspect ratio, so that a stressed capping layer is expected to be more effective for enhancing FinFET performance","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"120 1","pages":"988-991"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"25","resultStr":"{\"title\":\"Dual stress capping layer enhancement study for hybrid orientation finFET CMOS technology\",\"authors\":\"K. Shin, C. O. Chui, T. King\",\"doi\":\"10.1109/IEDM.2005.1609528\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"3D stress in FinFET and tri-gate FET structures induced by a tensile or compressive capping layer is studied via simulation. The classic bulk-Si piezoresistance model is then used to predict the impact on carrier mobilities. A tensile capping layer is expected to provide dramatic enhancements (>100%) in electron mobility for a (100)-sidewall fin with lang100rang current flow, while a compressive capping layer is expected to provide modest enhancement (<25%) in hole mobility for a (110)-sidewall fin with lang110rang current flow. Mobility enhancement will be greater for fins with higher aspect ratio, so that a stressed capping layer is expected to be more effective for enhancing FinFET performance\",\"PeriodicalId\":13071,\"journal\":{\"name\":\"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.\",\"volume\":\"120 1\",\"pages\":\"988-991\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"25\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2005.1609528\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2005.1609528","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Dual stress capping layer enhancement study for hybrid orientation finFET CMOS technology
3D stress in FinFET and tri-gate FET structures induced by a tensile or compressive capping layer is studied via simulation. The classic bulk-Si piezoresistance model is then used to predict the impact on carrier mobilities. A tensile capping layer is expected to provide dramatic enhancements (>100%) in electron mobility for a (100)-sidewall fin with lang100rang current flow, while a compressive capping layer is expected to provide modest enhancement (<25%) in hole mobility for a (110)-sidewall fin with lang110rang current flow. Mobility enhancement will be greater for fins with higher aspect ratio, so that a stressed capping layer is expected to be more effective for enhancing FinFET performance