S. C. Song, J. Xu, D. Yang, K. Rim, P. Feng, Jerry Bao, J. Zhu, J. Wang, G. Nallapati, M. Badaroglu, P. Narayanasetti, B. Bucki, J. Fischer, G. Yeap
{"title":"采用集成分析(UTOPIA)的统一技术优化平台,在<= 7nm节点上进行整体技术、设计和系统协同优化","authors":"S. C. Song, J. Xu, D. Yang, K. Rim, P. Feng, Jerry Bao, J. Zhu, J. Wang, G. Nallapati, M. Badaroglu, P. Narayanasetti, B. Bucki, J. Fischer, G. Yeap","doi":"10.1109/VLSIC.2016.7573515","DOIUrl":null,"url":null,"abstract":"We propose complete technology-design-system co-optimization method in which power, performance, thermal, area and cost metrics are all simultaneously optimized from transistor to mobile SOC system level. This novel method, Unified Technology Optimization Platform using Integrated Analysis (UTOPIA), incorporates thermally limited performance, wafer process complexity and die area scaling model in addition to author's previous transistor-interconnect optimization method. Thermal model in UTOPIA evaluates/optimizes device and technology parameters not only for peak frequency but also for sustained performance after thermal throttling. Optimum N7 technology is selected using proposed UTOPIA method, showing significant overall gain over N10 technology.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes\",\"authors\":\"S. C. Song, J. Xu, D. Yang, K. Rim, P. Feng, Jerry Bao, J. Zhu, J. Wang, G. Nallapati, M. Badaroglu, P. Narayanasetti, B. Bucki, J. Fischer, G. Yeap\",\"doi\":\"10.1109/VLSIC.2016.7573515\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose complete technology-design-system co-optimization method in which power, performance, thermal, area and cost metrics are all simultaneously optimized from transistor to mobile SOC system level. This novel method, Unified Technology Optimization Platform using Integrated Analysis (UTOPIA), incorporates thermally limited performance, wafer process complexity and die area scaling model in addition to author's previous transistor-interconnect optimization method. Thermal model in UTOPIA evaluates/optimizes device and technology parameters not only for peak frequency but also for sustained performance after thermal throttling. Optimum N7 technology is selected using proposed UTOPIA method, showing significant overall gain over N10 technology.\",\"PeriodicalId\":6512,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"volume\":\"1 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2016.7573515\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2016.7573515","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes
We propose complete technology-design-system co-optimization method in which power, performance, thermal, area and cost metrics are all simultaneously optimized from transistor to mobile SOC system level. This novel method, Unified Technology Optimization Platform using Integrated Analysis (UTOPIA), incorporates thermally limited performance, wafer process complexity and die area scaling model in addition to author's previous transistor-interconnect optimization method. Thermal model in UTOPIA evaluates/optimizes device and technology parameters not only for peak frequency but also for sustained performance after thermal throttling. Optimum N7 technology is selected using proposed UTOPIA method, showing significant overall gain over N10 technology.