通过HBM和TLP测试评估智能电源保护结构的ESD稳健性

2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059) Pub Date : 2000-04-10 DOI:10.1109/RELPHY.2000.843926

G. Meneghesso, S. Santirosi, E. Novarini, C. Contiero, E. Zanoni

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引用次数: 21

摘要

在本文中，我们将提供有关智能电源保护结构(采用双极、CMOS、DMOS、BCD技术制造)用于输入输出电路的ESD稳健性数据。比较了“p-体”结构和“p-井”结构的鲁棒性，并研究了布局参数对ESD鲁棒性的影响。还将介绍不同测试方法(HBM和TLP)获得的ESD稳健性之间的相关性。利用扫描电镜对器件的横截面进行了失效分析。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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ESD robustness of smart-power protection structures evaluated by means of HBM and TLP tests

In this paper we will present data concerning the ESD robustness of smart power protection structures (fabricated in Bipolar, CMOS, DMOS, BCD technology) for input-output circuits. A comparison between the robustness of "p-body" and "p-well" based structures and a study of the influence of layout parameters on the ESD robustness will be given. The correlation between ESD robustness obtained with different test methods (HBM and TLP) will be also presented. Failure analysis has been carried out by means of SEM device cross-sections.

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2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)

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