具有增益自适应列式adc和2对1堆叠器件结构的8.3 m像素480fps全局快门CMOS图像传感器

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI:10.1109/VLSIC.2016.7573543

Y. Oike, Kentaro Akiyama, Luong D. Hung, Wataru Niitsuma, A. Kato, Mamoru Sato, Yuri Kato, Wataru Nakamura, Hiroshi Shiroshita, Y. Sakano, Y. Kitano, Takuya Nakamura, T. Toyama, H. Iwamoto, T. Ezaki

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引用次数: 40

摘要

开发了一种4K2K 480 fps全快门CMOS图像传感器，采用超35mm格式。该传感器采用新开发的增益自适应列adc，在满量程读数为923 mV时，暗随机噪声为140 μVrms。在片上对两个可切换增益之间的误差进行在线校正，使输出图像的非线性保持在0.18%以内。16通道输出接口的速度为4.752 Gbps/ch，由2块逻辑芯片实现，堆叠在38K微凸点传感器芯片上。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An 8.3M-pixel 480fps global-shutter CMOS image sensor with gain-adaptive column ADCs and 2-on-1 stacked device structure

A 4K2K 480 fps global-shutter CMOS image sensor has been developed with super 35 mm format. This sensor employs newly developed gain-adaptive column ADCs to attain a dark random noise of 140 μVrms for the full-scale readout of 923 mV. An on-chip online correction of the error between two switchable gains maintains the nonlinearity of output image within 0.18 %. The 16-channel output interfaces with 4.752 Gbps/ch are implemented in 2 diced logic chips stacked on a sensor chip with 38K micro bumps.

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2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)

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