S. Ikeda, Hiroyuki Ito, A. Kasamatsu, Yosuke Ishikawa, T. Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, S. Hara, R. Dong, S. Dosho, N. Ishihara, K. Masu
{"title":"基于8.865 ghz−244dB-FOM高频压电谐振器的亚ppb级级分数n锁相环","authors":"S. Ikeda, Hiroyuki Ito, A. Kasamatsu, Yosuke Ishikawa, T. Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, S. Hara, R. Dong, S. Dosho, N. Ishihara, K. Masu","doi":"10.1109/VLSIC.2016.7573548","DOIUrl":null,"url":null,"abstract":"This paper proposes a high-frequency piezoelectric resonator (PZR)-based cascaded fractional-N PLL featuring channel adjusting technique with sub-ppb-order frequency resolution, which can overcome the difficulty using the narrow range GHz PZR. Moreover, undesirable oscillation induced by parasitic inductance of interconnects is suppressed by negative inductance technique. A power-efficient divider contributes to save power of the 2nd-PLL that suppresses output phase noise by the 1 GHz reference. The prototype PLL was fabricated in a 65nm CMOS and achieved 8.484GHz to 8.912GHz output, 180 fs rms-jitter, and -244 dB FOM while consuming 12.7mW.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"31 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"An 8.865-GHz −244dB-FOM high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique\",\"authors\":\"S. Ikeda, Hiroyuki Ito, A. Kasamatsu, Yosuke Ishikawa, T. Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, S. Hara, R. Dong, S. Dosho, N. Ishihara, K. Masu\",\"doi\":\"10.1109/VLSIC.2016.7573548\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a high-frequency piezoelectric resonator (PZR)-based cascaded fractional-N PLL featuring channel adjusting technique with sub-ppb-order frequency resolution, which can overcome the difficulty using the narrow range GHz PZR. Moreover, undesirable oscillation induced by parasitic inductance of interconnects is suppressed by negative inductance technique. A power-efficient divider contributes to save power of the 2nd-PLL that suppresses output phase noise by the 1 GHz reference. The prototype PLL was fabricated in a 65nm CMOS and achieved 8.484GHz to 8.912GHz output, 180 fs rms-jitter, and -244 dB FOM while consuming 12.7mW.\",\"PeriodicalId\":6512,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"volume\":\"31 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2016.7573548\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2016.7573548","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An 8.865-GHz −244dB-FOM high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique
This paper proposes a high-frequency piezoelectric resonator (PZR)-based cascaded fractional-N PLL featuring channel adjusting technique with sub-ppb-order frequency resolution, which can overcome the difficulty using the narrow range GHz PZR. Moreover, undesirable oscillation induced by parasitic inductance of interconnects is suppressed by negative inductance technique. A power-efficient divider contributes to save power of the 2nd-PLL that suppresses output phase noise by the 1 GHz reference. The prototype PLL was fabricated in a 65nm CMOS and achieved 8.484GHz to 8.912GHz output, 180 fs rms-jitter, and -244 dB FOM while consuming 12.7mW.