Daniel J. Connelly, Paul A. Clifton, C. Faulkner, D. Grupp
{"title":"到2018年,超薄体完全耗尽SOI金属源/漏n- mosfet和ITRS低备用功率目标","authors":"Daniel J. Connelly, Paul A. Clifton, C. Faulkner, D. Grupp","doi":"10.1109/IEDM.2005.1609524","DOIUrl":null,"url":null,"abstract":"Simulations of metal (Schottky) source/drain (S/D) ultra-thin-body fully depleted SOI n-channel MOSFETs, single and dual gate, were performed using parameters associated with ITRS LSTP targets for 2006 through 2018. By optimizing S/D-to-channel underlap for a given S/D barrier height, off-current can be reduced to match the ITRS LSTP specification for each year. ITRS on-current targets then establish limits on the S/D barrier height","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"4 1","pages":"972-975"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"Ultra-thin-body fully depleted SOI metal source/drain n-MOSFETs and ITRS low-standby-power targets through 2018\",\"authors\":\"Daniel J. Connelly, Paul A. Clifton, C. Faulkner, D. Grupp\",\"doi\":\"10.1109/IEDM.2005.1609524\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Simulations of metal (Schottky) source/drain (S/D) ultra-thin-body fully depleted SOI n-channel MOSFETs, single and dual gate, were performed using parameters associated with ITRS LSTP targets for 2006 through 2018. By optimizing S/D-to-channel underlap for a given S/D barrier height, off-current can be reduced to match the ITRS LSTP specification for each year. ITRS on-current targets then establish limits on the S/D barrier height\",\"PeriodicalId\":13071,\"journal\":{\"name\":\"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.\",\"volume\":\"4 1\",\"pages\":\"972-975\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2005.1609524\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2005.1609524","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Ultra-thin-body fully depleted SOI metal source/drain n-MOSFETs and ITRS low-standby-power targets through 2018
Simulations of metal (Schottky) source/drain (S/D) ultra-thin-body fully depleted SOI n-channel MOSFETs, single and dual gate, were performed using parameters associated with ITRS LSTP targets for 2006 through 2018. By optimizing S/D-to-channel underlap for a given S/D barrier height, off-current can be reduced to match the ITRS LSTP specification for each year. ITRS on-current targets then establish limits on the S/D barrier height