Ajit Sharma, Seung Bae Lee, Arup Polley, Sriram Narayanan, Wen Li, T. Sculley, S. Ramaswamy
{"title":"多模态智能生物传感SoC平台,具有>80dB信噪比35µA PPG RX链","authors":"Ajit Sharma, Seung Bae Lee, Arup Polley, Sriram Narayanan, Wen Li, T. Sculley, S. Ramaswamy","doi":"10.1109/VLSIC.2016.7573488","DOIUrl":null,"url":null,"abstract":"A multi-modal analog front end (AFE) and ultra-low energy bio-sensing CMOS SoC is presented. System/ circuit techniques enable signal path duty cycles as low as sub-1% and result in a 35μA Photo Plethysmography (PPG) RX Chain - 5X lower than published state of the art - while maintaining overall SNR > 80dBFS. The signal chain is adaptively synchronized by an ultra-low power FSM and includes a 1.3μW 14b 1kSPS SAR A/D. Input signal-aware, real-time data path adaptation is achieved by leveraging on-the-fly algorithms running on an external microcontroller (μC) to further reduce system energy. A programmable, asynchronous capacitive reset amplifier (PARCA) with NEF of 4.8 and dx/dt analog feature extractor demonstrate energy efficient ECG capture. A battery-powered, Bluetooth low energy (BLE) based, wearable platform with simultaneous ECG and PPG acquisition using this AFE has been demonstrated.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"65 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"Multi-modal smart bio-sensing SoC platform with >80dB SNR 35µA PPG RX chain\",\"authors\":\"Ajit Sharma, Seung Bae Lee, Arup Polley, Sriram Narayanan, Wen Li, T. Sculley, S. Ramaswamy\",\"doi\":\"10.1109/VLSIC.2016.7573488\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A multi-modal analog front end (AFE) and ultra-low energy bio-sensing CMOS SoC is presented. System/ circuit techniques enable signal path duty cycles as low as sub-1% and result in a 35μA Photo Plethysmography (PPG) RX Chain - 5X lower than published state of the art - while maintaining overall SNR > 80dBFS. The signal chain is adaptively synchronized by an ultra-low power FSM and includes a 1.3μW 14b 1kSPS SAR A/D. Input signal-aware, real-time data path adaptation is achieved by leveraging on-the-fly algorithms running on an external microcontroller (μC) to further reduce system energy. A programmable, asynchronous capacitive reset amplifier (PARCA) with NEF of 4.8 and dx/dt analog feature extractor demonstrate energy efficient ECG capture. A battery-powered, Bluetooth low energy (BLE) based, wearable platform with simultaneous ECG and PPG acquisition using this AFE has been demonstrated.\",\"PeriodicalId\":6512,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"volume\":\"65 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2016.7573488\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2016.7573488","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 16
摘要
提出了一种多模态模拟前端(AFE)和超低能量生物传感CMOS SoC。系统/电路技术使信号通路占空比低至低于1%,并产生35μA的光容积脉搏波(PPG) RX链-比目前公布的状态低5倍-同时保持总体信噪比> 80dBFS。信号链由超低功耗FSM自适应同步,包括1.3μW 14b 1kSPS SAR a /D。通过利用运行在外部微控制器(μC)上的动态算法来实现输入信号感知,实时数据路径自适应,以进一步降低系统能量。NEF为4.8的可编程异步电容复位放大器(PARCA)和dx/dt模拟特征提取器演示了高能效的心电捕获。一个基于电池供电、蓝牙低功耗(BLE)的可穿戴平台,使用该AFE同时进行ECG和PPG采集。
A multi-modal analog front end (AFE) and ultra-low energy bio-sensing CMOS SoC is presented. System/ circuit techniques enable signal path duty cycles as low as sub-1% and result in a 35μA Photo Plethysmography (PPG) RX Chain - 5X lower than published state of the art - while maintaining overall SNR > 80dBFS. The signal chain is adaptively synchronized by an ultra-low power FSM and includes a 1.3μW 14b 1kSPS SAR A/D. Input signal-aware, real-time data path adaptation is achieved by leveraging on-the-fly algorithms running on an external microcontroller (μC) to further reduce system energy. A programmable, asynchronous capacitive reset amplifier (PARCA) with NEF of 4.8 and dx/dt analog feature extractor demonstrate energy efficient ECG capture. A battery-powered, Bluetooth low energy (BLE) based, wearable platform with simultaneous ECG and PPG acquisition using this AFE has been demonstrated.