T. Sakata, S. Morita, O. Nagashima, H. Noda, T. Takahashi, T. Sonoda, H. Tadokoro, H. Ichikawa, T. Adou, S. Hanzawa, M. Ohi, S. Ookuma, Y. Suzuki, H. Tanaka, K. Ishii
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A DDR/SDR-compatible SDRAM design with a three-size flexible column redundancy
Two circuit techniques are proposed to design a SDRAM which operates both at a double-data-rate (DDR) and a single-data-rate (SDR). The common/separated I/O scheme enables 2-bit prefetching under a DDR and interrupt operations under an SDR with half the number of data-bus lines otherwise needed. The SSTL/LVTTL-compatible input buffer allows a narrow setup/hold time. Furthermore, the three-size flexible column redundancy enhances the yield. To evaluate these techniques, a 256-Mb SDRAM has been designed assuming 0.16-/spl mu/m technology and simulated with 167-MHz operations.
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