{"title":"一个114 pw的pmos，无微调电压基准，圆内误差0.26%，用于nW系统","authors":"Qing Dong, Kaiyuan Yang, D. Blaauw, D. Sylvester","doi":"10.1109/VLSIC.2016.7573494","DOIUrl":null,"url":null,"abstract":"A sub-nW voltage reference is presented that uses only PMOS transistors, thereby providing inherently low process variation and enabling trim-free operation for LDOs and other applications in nW microsystems. Sixty chips from 3 different wafers in 180nm CMOS are measured, showing an untrimmed within-wafer σ/μ of 0.26% and wafer-to-wafer σ/μ of 1.9%. Measurement results also show a temperature coefficient of 48-124ppm/°C from -40°C to 85°C. Outputting a 0.986V reference voltage, the reference operates down to 1.2V and consumes 114pW at 25°C.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"36 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"50","resultStr":"{\"title\":\"A 114-pW PMOS-only, trim-free voltage reference with 0.26% within-wafer inaccuracy for nW systems\",\"authors\":\"Qing Dong, Kaiyuan Yang, D. Blaauw, D. Sylvester\",\"doi\":\"10.1109/VLSIC.2016.7573494\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A sub-nW voltage reference is presented that uses only PMOS transistors, thereby providing inherently low process variation and enabling trim-free operation for LDOs and other applications in nW microsystems. Sixty chips from 3 different wafers in 180nm CMOS are measured, showing an untrimmed within-wafer σ/μ of 0.26% and wafer-to-wafer σ/μ of 1.9%. Measurement results also show a temperature coefficient of 48-124ppm/°C from -40°C to 85°C. Outputting a 0.986V reference voltage, the reference operates down to 1.2V and consumes 114pW at 25°C.\",\"PeriodicalId\":6512,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"volume\":\"36 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"50\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2016.7573494\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2016.7573494","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 114-pW PMOS-only, trim-free voltage reference with 0.26% within-wafer inaccuracy for nW systems
A sub-nW voltage reference is presented that uses only PMOS transistors, thereby providing inherently low process variation and enabling trim-free operation for LDOs and other applications in nW microsystems. Sixty chips from 3 different wafers in 180nm CMOS are measured, showing an untrimmed within-wafer σ/μ of 0.26% and wafer-to-wafer σ/μ of 1.9%. Measurement results also show a temperature coefficient of 48-124ppm/°C from -40°C to 85°C. Outputting a 0.986V reference voltage, the reference operates down to 1.2V and consumes 114pW at 25°C.
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