A Compact Ferroelectric 2T-(n+1)C Cell to Implement AND-OR Logic in Memory

Abstract

With the proliferation of data-intensive applications, various logic-in-memory (LIM)/ in-memory computing (IMC) solutions are emerging. These solutions aim to mitigate the von Neumann bottleneck caused by frequent data transfer between computational units and memory arrays. Ferroelectric devices such as ferroelectric random access memory (FeRAM), ferroelectric FET (FeFET) and ferroelectric tunnel junction (FTJ) etc., are promising nonvolatile memory (NVM) candidates for the LIM application due to their lower write power compared to competing NVM technologies. In this work, we propose a compact ferroelectric 2T-(n+1) C LIM cell to implement ANDOR logic based on the concept of quasi-nondestructive readout (QNRO) FeRAM. In comparison with 1T-1C FeRAM and 1T FeFET, our structure has both distinguished write and read characteristics. The n-bit AND-OR logic accomplished by our design has $2\mathrm{n}\times$ performance improvement and $5.1\times$ integration density gain against the conventional CMOS logic. Additionally, the area efficiency of our design can be further enhanced by 3D integration. We then verify the correctness of a 3-bit AND-OR logic gate by conducting circuit simulation and device experiments. The simulation results demonstrate a $\sim 70$ ON/OFF ratio with the ON/OFF current window of $\gt866\mathrm{nA}$, and for the experimental results the $\mathrm{ON}/\mathrm{OFF}$ ratio is 3.8 with the current window of $\gt68\mu\mathrm{A}$.