CellFlow: Automated Standard Cell Design Flow

Abstract

The existing flow for creating standard cell library is industry protected, with minimum options to tweak and improve the cell properties. Open-Source ASIC tools are constantly emerging. However, the existing flow does not offer any options for the realization of custom cells. Hence a novel and reliable custom standard cell library flow integrated with a robust optimization scheme referred to as CellFlow is introduced to establish custom cell design. Cartesian genetic programming (CGP), an evolutionary algorithm, was employed to generate optimized and hardware efficient transistor level designs to incorporate in the standard cell flow. The CGP algorithm is configured to render the fewest count transistor custom standard cell designs, which are then characterized for hardware metrics, including power, delay, area, and layout. Further particle-swarm-optimization (PSO) method was adopted to optimize the spice netlist evolved from the CGP synthesized transistor-level design. The CellFlow was employed to develop custom standard cells, including compressors, full-adders, multipliers, and multiplexers designs. The developed custom standard cell library was validated for 4$\times$ 4 Systolic array architecture and PICO-RV32 RISCV core design, showing expected synthesized results.