Revisiting Trojan Insertion Techniques for Post-Silicon Trojan Detection Evaluation

Abstract

The distributed supply chain of the semiconductor industry has promoted several attacks at different stages of Integrated Circuit (IC) design and manufacturing. Hardware Trojans (HTs) injected into the IC by a malicious foundry can lead to catastrophic consequences. Recent research efforts have shown the power of reinforcement learning not only in detecting HTs but also bypassing these detection mechanisms. However, they do not take into account the detailed circuit structural information. In this paper, we explore different new strategies for triggering HTs to evaluate the most recently proposed post-silicon HT detection techniques. Specifically, we develop different automated and scalable rare net selection techniques to construct HT trigger conditions informed by the circuit structure. We evaluate our approaches for different benchmarks against the most recently proposed reinforcement learning and other state-of-the-art logic testing HT detection techniques.