A Low Power Dynamic Comparator For A 12-Bit Pipelined Successive Approximation Register (SAR) ADC

Abstract

210MS/s 12-bit pipelined SAR ADC that can be used for mobile applications consists of various components that can reduce the precision and the power consumption of the device. It has been identified that the main component that causes a high power consumption in the circuit design is the dynamic comparator. The proposed design of the dynamic comparator shows a double tail dynamic comparator with an output buffer, which creates an impedance that can reduce the power consumption of the circuit considerably. The maximum power consumption of the comparator used is measured to be 402.3pW.