Pub Date : 2018-03-16DOI: 10.1109/ICDCSYST.2018.8605145
Naman Gupta, P. Goyal, Kavindra Kandpal, K. R. Teja
In this paper, we have compared and analyzed two architectures of implicit pulsed triggered flip-flop (P-FF). The Predictive Technology Model (PTM) 45nm and 32nm technology nodes are used for simulations. The variation in delay and power for both architectures with respect to variation in supply voltage (VDD) and temperature is analyzed. Results from simulations at 45nm show that design with conditional pulse-enhancement technique (CPE) is better in terms of power consumption whereas design using gated-pull up control (GPC) is less prone to temperature and supply voltage variation. Similar trends have been noticed at a 32nm technology node.
{"title":"A Comparative Study of Pulse Triggered Flipflops","authors":"Naman Gupta, P. Goyal, Kavindra Kandpal, K. R. Teja","doi":"10.1109/ICDCSYST.2018.8605145","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605145","url":null,"abstract":"In this paper, we have compared and analyzed two architectures of implicit pulsed triggered flip-flop (P-FF). The Predictive Technology Model (PTM) 45nm and 32nm technology nodes are used for simulations. The variation in delay and power for both architectures with respect to variation in supply voltage (VDD) and temperature is analyzed. Results from simulations at 45nm show that design with conditional pulse-enhancement technique (CPE) is better in terms of power consumption whereas design using gated-pull up control (GPC) is less prone to temperature and supply voltage variation. Similar trends have been noticed at a 32nm technology node.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116798031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-16DOI: 10.1109/ICDCSYST.2018.8605173
S. P, Aijaz A. Khan
In this paper the concept that is used is power efficient multipliers which are very important part of all VLSI system design which provides High speed with low power consumption which are the key requirements for any VLSI design. This paper proposes an efficient implementation of a high speed with low power multiplier using shift and adds methods and this paper presents the implementation of Braun multiplier and Wallace Multiplier using Cadence (Encounter) RTL Complier with simulation which includes creating the Test circuit for each block that is combined together which forms Multiplier. In this paper, Braun Multiplier and Wallace multiplier are simulated by creating the schematic circuit for each of the building blocks such as the AND gate, OR gate, NOT gate, EXOR gate, Half Adder, Full adder and are tested using a test circuit for each of the above blocks. These test circuits are simulated and synthesized using the Cadence tool. Symbol for these building blocks are generated and are called to construct the structure of Braun Multiplier and Wallace Multiplier. Then the multipliers are compared with respect to the number of transistors used which will provide the area occupied and power consumed. Cadence software is used to implement the schematic circuits of each block and all the blocks are simulated using cadence tool and also symbols are created which are assembled together to form a test circuit and all the analysis are tested and also synthesized using Cadence
{"title":"Comparison of Braun Multiplier and Wallace Multiplier Techniques in VLSI","authors":"S. P, Aijaz A. Khan","doi":"10.1109/ICDCSYST.2018.8605173","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605173","url":null,"abstract":"In this paper the concept that is used is power efficient multipliers which are very important part of all VLSI system design which provides High speed with low power consumption which are the key requirements for any VLSI design. This paper proposes an efficient implementation of a high speed with low power multiplier using shift and adds methods and this paper presents the implementation of Braun multiplier and Wallace Multiplier using Cadence (Encounter) RTL Complier with simulation which includes creating the Test circuit for each block that is combined together which forms Multiplier. In this paper, Braun Multiplier and Wallace multiplier are simulated by creating the schematic circuit for each of the building blocks such as the AND gate, OR gate, NOT gate, EXOR gate, Half Adder, Full adder and are tested using a test circuit for each of the above blocks. These test circuits are simulated and synthesized using the Cadence tool. Symbol for these building blocks are generated and are called to construct the structure of Braun Multiplier and Wallace Multiplier. Then the multipliers are compared with respect to the number of transistors used which will provide the area occupied and power consumed. Cadence software is used to implement the schematic circuits of each block and all the blocks are simulated using cadence tool and also symbols are created which are assembled together to form a test circuit and all the analysis are tested and also synthesized using Cadence","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123783570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-16DOI: 10.1109/ICDCSYST.2018.8605118
M. Chakraverty, P. Harisankar
This paper reports the bias dependence of tunneling magnetoresistance in Co-MgO-Co magnetic tunnel junctions (MTJs) using first principles SGGA band structure calculations at four different temperatures. The Co-MgO-Co tunnel junction has been simulated at four different temperatures to obtain the I-V and dI/dV-V characteristics with parallel and anti-parallel magnetization states, respectively. The TMR ratios have been computed at all four different temperatures. It is seen that temperature doesn't seem to greatly fluctuate the TMR ratios of this magnetic tunnel junction, thereby making it suitable for applications over a wide range of temperatures. For the same four temperatures, the tunnel junction has been simulated for increasing insulator thicknesses. The exponential increase in resistance in both parallel and antiparallel magnetization states has been observed with an increase in the insulating layer thickness. The effect of increasing insulator thicknesses on the TMR ratios at all the four temperatures has also been presented in this paper. The demonstration of bias dependence of tunneling magnetoresistance presented in this paper aptly justifies the application of Co-MgO-Co MTJs in Magnetoresistive Random Access Memories.
{"title":"Demonstration of Bias Dependence of Tunnel Magnetoresistance in Co-MgO-Co Magnetic Tunnel Junctions using First Principles Calculations","authors":"M. Chakraverty, P. Harisankar","doi":"10.1109/ICDCSYST.2018.8605118","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605118","url":null,"abstract":"This paper reports the bias dependence of tunneling magnetoresistance in Co-MgO-Co magnetic tunnel junctions (MTJs) using first principles SGGA band structure calculations at four different temperatures. The Co-MgO-Co tunnel junction has been simulated at four different temperatures to obtain the I-V and dI/dV-V characteristics with parallel and anti-parallel magnetization states, respectively. The TMR ratios have been computed at all four different temperatures. It is seen that temperature doesn't seem to greatly fluctuate the TMR ratios of this magnetic tunnel junction, thereby making it suitable for applications over a wide range of temperatures. For the same four temperatures, the tunnel junction has been simulated for increasing insulator thicknesses. The exponential increase in resistance in both parallel and antiparallel magnetization states has been observed with an increase in the insulating layer thickness. The effect of increasing insulator thicknesses on the TMR ratios at all the four temperatures has also been presented in this paper. The demonstration of bias dependence of tunneling magnetoresistance presented in this paper aptly justifies the application of Co-MgO-Co MTJs in Magnetoresistive Random Access Memories.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"436 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132830649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-16DOI: 10.1109/ICDCSYST.2018.8605142
Akshat, Gaurav, Zahid, Bhupendra, Aditi, Sachin Kumar, Maneesha, P. Pandey
The present work proposes an efficient architecture of a smart health care monitoring framework using sensors and Internet of Things. With 1: 1674 doctor-patient population ratio in India, the shortage of health providers and infrastructure is the most acute in rural areas. The paper presents an efficient model wherein a doctor can monitor the health of the patient from a remote location through the efficient use of technology, thereby addressing this shortage of healthcare personal in Indian scenario. In the proposed system, the vital health parameters like Electrocardiograph (ECG), Body Temperature, Blood Pressure (BP), Heart Beat rate, Glucose Level Detection and Galvanic Skin Response of patient are collected and evaluated through the use of smart devices. The data is further transmitted wirelessly through Zigbee IEEE 801.15.4 technology for further analysis using data analytics. Next the android application of the system displays this data about vital statistics on a Smartphone of a doctor enabling him to receive the current status of the patient without being physically present there. Whenever there is a variation in any physiological parameter of a patient beyond a pre-assigned threshold value, an automated notification will pop up in doctors’ android mobile application. Hence the present IOT based smart health care monitoring system enables the remote monitoring of medical parameters along with the tracking of medical equipments leading to smart hospital services.
{"title":"A Smart Healthcare Monitoring System Using Smartphone Interface","authors":"Akshat, Gaurav, Zahid, Bhupendra, Aditi, Sachin Kumar, Maneesha, P. Pandey","doi":"10.1109/ICDCSYST.2018.8605142","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605142","url":null,"abstract":"The present work proposes an efficient architecture of a smart health care monitoring framework using sensors and Internet of Things. With 1: 1674 doctor-patient population ratio in India, the shortage of health providers and infrastructure is the most acute in rural areas. The paper presents an efficient model wherein a doctor can monitor the health of the patient from a remote location through the efficient use of technology, thereby addressing this shortage of healthcare personal in Indian scenario. In the proposed system, the vital health parameters like Electrocardiograph (ECG), Body Temperature, Blood Pressure (BP), Heart Beat rate, Glucose Level Detection and Galvanic Skin Response of patient are collected and evaluated through the use of smart devices. The data is further transmitted wirelessly through Zigbee IEEE 801.15.4 technology for further analysis using data analytics. Next the android application of the system displays this data about vital statistics on a Smartphone of a doctor enabling him to receive the current status of the patient without being physically present there. Whenever there is a variation in any physiological parameter of a patient beyond a pre-assigned threshold value, an automated notification will pop up in doctors’ android mobile application. Hence the present IOT based smart health care monitoring system enables the remote monitoring of medical parameters along with the tracking of medical equipments leading to smart hospital services.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133077018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-16DOI: 10.1109/ICDCSYST.2018.8605167
Hema Mehta, H. Kaur
In the present work, the impact of high-k spacers and Negative Capacitance (NC) has been examined on the performance of nanoscale Double Gate Junctionless Transistors by self consistently solving Landau Khalatnikov equation with TCAD simulations. Ferroelectric hafnium oxide is considered in gate stack with interfacial layer of silicon dioxide. The impact of different dielectric constants of spacer and different spacer lengths have been explored extensively on various electrical parameters. It has been demonstrated that high-k spacers significantly improve the gate controllability, thereby, further enhancing the negative capacitance (NC) effect of ferroelectric layer on device operation. The subthreshold swing values as low as 10mV/dec have been obtained along with substantial improvement in Ion/Ioff ratio (about 3 orders), thereby, indicating suitability of the device for future ultra low power electronic applications.
{"title":"Impact of High-k spacer and Negative Capacitance on Double Gate Junctionless Transistor for Improved Short Channel Immunity and Reliability","authors":"Hema Mehta, H. Kaur","doi":"10.1109/ICDCSYST.2018.8605167","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605167","url":null,"abstract":"In the present work, the impact of high-k spacers and Negative Capacitance (NC) has been examined on the performance of nanoscale Double Gate Junctionless Transistors by self consistently solving Landau Khalatnikov equation with TCAD simulations. Ferroelectric hafnium oxide is considered in gate stack with interfacial layer of silicon dioxide. The impact of different dielectric constants of spacer and different spacer lengths have been explored extensively on various electrical parameters. It has been demonstrated that high-k spacers significantly improve the gate controllability, thereby, further enhancing the negative capacitance (NC) effect of ferroelectric layer on device operation. The subthreshold swing values as low as 10mV/dec have been obtained along with substantial improvement in Ion/Ioff ratio (about 3 orders), thereby, indicating suitability of the device for future ultra low power electronic applications.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126856840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-16DOI: 10.1109/ICDCSYST.2018.8605124
Preeti Singh, V. Kumari, M. Saxena, Mridula Gupta
In this paper, simulation study has been carried out to evaluate the impact of high-k gate dielectric on DC performance of Dual-Gate MISHEMTs. Comparison of different gate dielectrics and gate stacks such as $mathrm {S}mathrm {i}_{3}mathrm {N}_{4}, mathrm {A}1_{2}mathrm {O}_{3}, mathrm {H}mathrm {f}mathrm {O}_{2}, mathrm {A}1_{2}mathrm {O}_{3}/mathrm {S}mathrm {i}_{3}mathrm {N}_{4}, mathrm {H}mathrm {f}mathrm {O}_{2}/mathrm {S}mathrm {i}_{3}mathrm {N}_{4}$ and $mathrm {H}mathrm {f}mathrm {O}_{2}/mathrm {A}1_{2}mathrm {O}_{3}$ has been presented. Threshold voltage shift of 10.6% has been observed for $mathrm {H}mathrm {f}mathrm {O}_{2}/mathrm {A}1_{2}mathrm {O}_{3}$ gate dielectric stack for DG-MISHEMT if interface charge density were varied from $4.6times 10^{12}mathrm {c}mathrm {m}^{-2}$ to $8times 10^{12}mathrm {c}mathrm {m}^{-2}$ and this shift is minimum as compared to other gate stacks combinations like $mathrm {A}1_{2}mathrm {O}_{3}/mathrm {S}mathrm {i}_{3}mathrm {N}_{4}$ or $mathrm {H}mathrm {f}mathrm {O}_{2}/mathrm {S}mathrm {i}_{3}mathrm {N}_{4}$. Also, threshold voltage change is marginal with different stack thickness variation. Simulations were carried out using ATLAS module of SILVACO TCAD tool at ambient temperature.
{"title":"Optimization of Gate Oxide of Dual-Gate MISHEMTs for Enhanced DC performance","authors":"Preeti Singh, V. Kumari, M. Saxena, Mridula Gupta","doi":"10.1109/ICDCSYST.2018.8605124","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605124","url":null,"abstract":"In this paper, simulation study has been carried out to evaluate the impact of high-k gate dielectric on DC performance of Dual-Gate MISHEMTs. Comparison of different gate dielectrics and gate stacks such as $mathrm {S}mathrm {i}_{3}mathrm {N}_{4}, mathrm {A}1_{2}mathrm {O}_{3}, mathrm {H}mathrm {f}mathrm {O}_{2}, mathrm {A}1_{2}mathrm {O}_{3}/mathrm {S}mathrm {i}_{3}mathrm {N}_{4}, mathrm {H}mathrm {f}mathrm {O}_{2}/mathrm {S}mathrm {i}_{3}mathrm {N}_{4}$ and $mathrm {H}mathrm {f}mathrm {O}_{2}/mathrm {A}1_{2}mathrm {O}_{3}$ has been presented. Threshold voltage shift of 10.6% has been observed for $mathrm {H}mathrm {f}mathrm {O}_{2}/mathrm {A}1_{2}mathrm {O}_{3}$ gate dielectric stack for DG-MISHEMT if interface charge density were varied from $4.6times 10^{12}mathrm {c}mathrm {m}^{-2}$ to $8times 10^{12}mathrm {c}mathrm {m}^{-2}$ and this shift is minimum as compared to other gate stacks combinations like $mathrm {A}1_{2}mathrm {O}_{3}/mathrm {S}mathrm {i}_{3}mathrm {N}_{4}$ or $mathrm {H}mathrm {f}mathrm {O}_{2}/mathrm {S}mathrm {i}_{3}mathrm {N}_{4}$. Also, threshold voltage change is marginal with different stack thickness variation. Simulations were carried out using ATLAS module of SILVACO TCAD tool at ambient temperature.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130583519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-16DOI: 10.1109/ICDCSYST.2018.8605077
S. Sridevi sathya priya, M. Junias, S. Sarah Jenifer, A. Lavanya
The National Institute of Standards and Technology(NIST) announced Rijndael as the new Advanced Encryption Standard(AES). DES algorithm was the predecessor of AES algorithm which was insecure because of force attacks. The AES is a symmetric block cipher. This encryption process consists of key expansion, Add Round Key, sub bytes, Shift Rows and mix column. This paper presents the survey of efficient cryptographic algorithms and implementation of efficient Mix Column in AES algorithm. Mix column transformation is the linear operation in which the state array matrix is multiplied with constant square matrix. LUT architecture is to be introduced in Mix Column in order to reduce the area. Also pipelining architecture is to be introduced in order to reduce the de;ay since the multiplication is the slow process which in-tum reduces the speed of whole AES encryption process.
{"title":"Implementation of Efficient Mix Column Transformation for AES encryption","authors":"S. Sridevi sathya priya, M. Junias, S. Sarah Jenifer, A. Lavanya","doi":"10.1109/ICDCSYST.2018.8605077","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605077","url":null,"abstract":"The National Institute of Standards and Technology(NIST) announced Rijndael as the new Advanced Encryption Standard(AES). DES algorithm was the predecessor of AES algorithm which was insecure because of force attacks. The AES is a symmetric block cipher. This encryption process consists of key expansion, Add Round Key, sub bytes, Shift Rows and mix column. This paper presents the survey of efficient cryptographic algorithms and implementation of efficient Mix Column in AES algorithm. Mix column transformation is the linear operation in which the state array matrix is multiplied with constant square matrix. LUT architecture is to be introduced in Mix Column in order to reduce the area. Also pipelining architecture is to be introduced in order to reduce the de;ay since the multiplication is the slow process which in-tum reduces the speed of whole AES encryption process.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132559079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-16DOI: 10.1109/ICDCSYST.2018.8605064
R. James, Ajith Ravindran
Out of many adders like Ripple carry adder, carry look ahead adder, carry select adder and prefix adder, kogge stone adder is a high performance adder and also less affected by errors. Kogge stone adder is an advanced version of parallel prefix adders and also consists of less number of components thus delay is reduced. It consumes less power when compared with other adders, but it might consists of leakage current because of increase in stand-by power in the circuit. Leakage current is introduced in the circuit because of scaling of transistors. Thus VLSI designers found it difficult to reduce the parameters such as delay, power, area and leakage current simultaneously. To overcome this disadvantage, an MTJ(Magnetic Tunnel Juction) is introduced in the CMOS circuits. By the use of MTJs in the circuit the leakage current is reduced and zero standby power is obtained. A comparison analysis is done between a hybrid 4-bit MTJ/CMOS based full adder and 4-bit Kogge stone adder.
{"title":"Review of Full Adder Performance Analysis Using Kogge Stone Adder and Magnetic Tunnel Junction","authors":"R. James, Ajith Ravindran","doi":"10.1109/ICDCSYST.2018.8605064","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605064","url":null,"abstract":"Out of many adders like Ripple carry adder, carry look ahead adder, carry select adder and prefix adder, kogge stone adder is a high performance adder and also less affected by errors. Kogge stone adder is an advanced version of parallel prefix adders and also consists of less number of components thus delay is reduced. It consumes less power when compared with other adders, but it might consists of leakage current because of increase in stand-by power in the circuit. Leakage current is introduced in the circuit because of scaling of transistors. Thus VLSI designers found it difficult to reduce the parameters such as delay, power, area and leakage current simultaneously. To overcome this disadvantage, an MTJ(Magnetic Tunnel Juction) is introduced in the CMOS circuits. By the use of MTJs in the circuit the leakage current is reduced and zero standby power is obtained. A comparison analysis is done between a hybrid 4-bit MTJ/CMOS based full adder and 4-bit Kogge stone adder.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127054856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-16DOI: 10.1109/ICDCSYST.2018.8605119
D. Moni, A. Anucia, D. Gracia, D. Nirmal
The scaling limitations of conventional MOSFET necessitates new MOS device architecture that can operate at low voltage for low power applications. III-V heterojunction TFET has been created and its performance has been studied. The analysis has been made to choose proper values to source and drain regions doping and work functions for the gate metal electrodes. Tunnel FET device attains 51 mV/dec subthreshold swing with $I_{ON}=1.96times 10^{-5}A;I_{OFF}=8.217times 10^{-12}$ A.
{"title":"Performance Analysis of GaSb/InAs Tunnel FET for Low Power Applications","authors":"D. Moni, A. Anucia, D. Gracia, D. Nirmal","doi":"10.1109/ICDCSYST.2018.8605119","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605119","url":null,"abstract":"The scaling limitations of conventional MOSFET necessitates new MOS device architecture that can operate at low voltage for low power applications. III-V heterojunction TFET has been created and its performance has been studied. The analysis has been made to choose proper values to source and drain regions doping and work functions for the gate metal electrodes. Tunnel FET device attains 51 mV/dec subthreshold swing with $I_{ON}=1.96times 10^{-5}A;I_{OFF}=8.217times 10^{-12}$ A.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127834502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-16DOI: 10.1109/ICDCSYST.2018.8605146
S. R. Jino Ramson, Deepthi Bhavanam, Srirupa Draksharam, anjeet Kumar, D. Jackuline Moni, A. Alfred Kirubaraj
Intensive fish culture involves fostering fish in farms, tanks or some enclosures, usually for food. Water quality monitoring systems play an important role in modern intensive fish culture. Various water quality parameters such as temperature, pH, dissolved oxygen, electrical conductivity, etc need to be measured and controlled from time to time in order to ensure proper growth of fish. Real time monitoring of fish farm allows the farmers to be aware of the various water quality parameters and helps to ensure the health of fishes. This paper presents the review of various sensor networks based real-time water quality monitoring systems with an insight of advanced researches in the field of fish culture.
{"title":"Sensor Networks based Water Quality Monitoring Systems for Intensive Fish Culture -A Review","authors":"S. R. Jino Ramson, Deepthi Bhavanam, Srirupa Draksharam, anjeet Kumar, D. Jackuline Moni, A. Alfred Kirubaraj","doi":"10.1109/ICDCSYST.2018.8605146","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2018.8605146","url":null,"abstract":"Intensive fish culture involves fostering fish in farms, tanks or some enclosures, usually for food. Water quality monitoring systems play an important role in modern intensive fish culture. Various water quality parameters such as temperature, pH, dissolved oxygen, electrical conductivity, etc need to be measured and controlled from time to time in order to ensure proper growth of fish. Real time monitoring of fish farm allows the farmers to be aware of the various water quality parameters and helps to ensure the health of fishes. This paper presents the review of various sensor networks based real-time water quality monitoring systems with an insight of advanced researches in the field of fish culture.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125596186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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