P. Thorel, J. Rainard, A. Botta, A. Chemarin, J. Majos
{"title":"IMPLEMENTING BOUNDARY-SCAN AND PSEUDO-RANDOM BIST IN AN ASYNCHRONOUS TRANSFER MODE SWITCH","authors":"P. Thorel, J. Rainard, A. Botta, A. Chemarin, J. Majos","doi":"10.1109/TEST.1991.519503","DOIUrl":null,"url":null,"abstract":"&pact : This paper shows how the features of both Boundary-Scan and Pseudo-Random BIST (Built-In Self Test) approaches go well together, implemented on a VLSI circuit devoted to telecommunications. The chosen circuit is a 0.7 p CMOS Asynchronous Transfer Mode (ATAI) switch of 350,000 transistors, for use in a 16 x 16 ATM Switching Matrix able to run at a throughpuu rate of up to 1.244 Gbitls. First, the nominal circuit is presented. Then the test approaches used are evoked, before discussing the main test problems encountered. The paper concludes with concrete results, validating tk chosen approaches and their applications in such a large circuit.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"18 3","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1991, Proceedings. International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.1991.519503","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
&pact : This paper shows how the features of both Boundary-Scan and Pseudo-Random BIST (Built-In Self Test) approaches go well together, implemented on a VLSI circuit devoted to telecommunications. The chosen circuit is a 0.7 p CMOS Asynchronous Transfer Mode (ATAI) switch of 350,000 transistors, for use in a 16 x 16 ATM Switching Matrix able to run at a throughpuu rate of up to 1.244 Gbitls. First, the nominal circuit is presented. Then the test approaches used are evoked, before discussing the main test problems encountered. The paper concludes with concrete results, validating tk chosen approaches and their applications in such a large circuit.
本文展示了边界扫描和伪随机BIST(内置自我测试)方法的特点如何很好地结合在一起，在专用于电信的VLSI电路上实现。所选择的电路是一个由35万个晶体管组成的0.7 p CMOS异步传输模式(ATAI)开关，用于16 x 16 ATM交换矩阵，能够以高达1.244 gbit / s的通流率运行。首先，给出了标称电路。然后回顾了常用的测试方法，讨论了测试中遇到的主要问题。最后给出了具体的结果，验证了所选方法及其在大型电路中的应用。
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