Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519494
T. Kropf, H. Wunderlich
Hardware verifrcation and sequential test generation are aspects of the same problem, namely to prove the equal behavior determined by two circuit descriptions. During test generation, this attempt succeeds for the faulty and fault free circuit if redundancy exists, and during verifrcation it succeeds, if the implementation is correct with regard to its specification. This observation can be used to cross-fertilize both areas, which have been treated separately up to now. In this work, a common formal pamework for hardware verification and sequential test pattern generation is presented, which is based on modeling the circuit behavior with temporal logic. In addition, a new approach to cope with non resetable flipfiops in sequential test generation is proposed, which is not restricted to stuck-at faults. Based on this verification view, it is possible to provide the designer with one tool for checking circuit correctness and generating test patterns. Its first implementation and application is also described.
{"title":"A common approach to test generation and hardware verification based on temporal logic","authors":"T. Kropf, H. Wunderlich","doi":"10.1109/TEST.1991.519494","DOIUrl":"https://doi.org/10.1109/TEST.1991.519494","url":null,"abstract":"Hardware verifrcation and sequential test generation are aspects of the same problem, namely to prove the equal behavior determined by two circuit descriptions. During test generation, this attempt succeeds for the faulty and fault free circuit if redundancy exists, and during verifrcation it succeeds, if the implementation is correct with regard to its specification. This observation can be used to cross-fertilize both areas, which have been treated separately up to now. In this work, a common formal pamework for hardware verification and sequential test pattern generation is presented, which is based on modeling the circuit behavior with temporal logic. In addition, a new approach to cope with non resetable flipfiops in sequential test generation is proposed, which is not restricted to stuck-at faults. Based on this verification view, it is possible to provide the designer with one tool for checking circuit correctness and generating test patterns. Its first implementation and application is also described.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114650375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519726
R. Aitken
Recently there has been renewed interest in fault detection in static CMOS circuits through current monitoring (“Iddq testing”). It is shown that accurate defect (diagnosis miay be performed with a combination of current and voltage observations. The proposed system combines a simple single fault model for test generation with a more realistic multiple defect model for diagnosis. ‘The associated hardware is sufficiently simple that on-board implementation is possible.
{"title":"Fault Location with Current Monitoring","authors":"R. Aitken","doi":"10.1109/TEST.1991.519726","DOIUrl":"https://doi.org/10.1109/TEST.1991.519726","url":null,"abstract":"Recently there has been renewed interest in fault detection in static CMOS circuits through current monitoring (“Iddq testing”). It is shown that accurate defect (diagnosis miay be performed with a combination of current and voltage observations. The proposed system combines a simple single fault model for test generation with a more realistic multiple defect model for diagnosis. ‘The associated hardware is sufficiently simple that on-board implementation is possible.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125939570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519732
M. Franklin, K. Saluja
State-of-the-art memory chips are designed with spare rows and columns for reconfiguration purposes. After a memory chip is reconfigured, physically adjacent cells may no longer have consecutive logical addresses. Test algorithms used at later stages for the detection of physical neighborhood pattern sensitive faults have to consider the fact that the address mapping of the memory chip is no longer available. Furthermore, RAM decoders are designed with a view to minimize the overall silicon area and critical path lengths. This can also result in designs in which physically adjacent rows (and columns) are not logically adjacent. In this paper, we present new test algorithms to detect 5-cell and 9-cell physical neighborhood pattern sensitive faults in dynamic RAMs, even if the logical and physical addresses are different and the physical-to-logical address mapping is not available. These algorithms have test lengths of O(Nr10g3M4) for N-bit RAMs, and also detect other faults such as stuck-at and coupling faults. The algorithms depend on the development of an efficient 3-coloring algorithm that michromatically colors all the triplets among a group off n objects in at most r1og34 coloring steps.
{"title":"AN ALGORITHM TO TEST RAMS FOR PHYSICAL NEIGHBORHOOD PATTERN SENSITIVE FAULTS","authors":"M. Franklin, K. Saluja","doi":"10.1109/TEST.1991.519732","DOIUrl":"https://doi.org/10.1109/TEST.1991.519732","url":null,"abstract":"State-of-the-art memory chips are designed with spare rows and columns for reconfiguration purposes. After a memory chip is reconfigured, physically adjacent cells may no longer have consecutive logical addresses. Test algorithms used at later stages for the detection of physical neighborhood pattern sensitive faults have to consider the fact that the address mapping of the memory chip is no longer available. Furthermore, RAM decoders are designed with a view to minimize the overall silicon area and critical path lengths. This can also result in designs in which physically adjacent rows (and columns) are not logically adjacent. In this paper, we present new test algorithms to detect 5-cell and 9-cell physical neighborhood pattern sensitive faults in dynamic RAMs, even if the logical and physical addresses are different and the physical-to-logical address mapping is not available. These algorithms have test lengths of O(Nr10g3M4) for N-bit RAMs, and also detect other faults such as stuck-at and coupling faults. The algorithms depend on the development of an efficient 3-coloring algorithm that michromatically colors all the triplets among a group off n objects in at most r1og34 coloring steps.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114925009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519728
Partha Raghavachari
We describe a VLSI device used in AT&:T StarServerTM products that provid.ea hamdware EiIST at the circuit board level. It integrakes memory control, error regulation and test functions for memory arrays. Programmable memory test algorithms may be invoked by the system user. A factory interface to the BIST facility is provided through boundary scam.
{"title":"CIRCUIT PACK BIST FROM SYSTEM TO FACTORY - THE MCERT CHIP","authors":"Partha Raghavachari","doi":"10.1109/TEST.1991.519728","DOIUrl":"https://doi.org/10.1109/TEST.1991.519728","url":null,"abstract":"We describe a VLSI device used in AT&:T StarServerTM products that provid.ea hamdware EiIST at the circuit board level. It integrakes memory control, error regulation and test functions for memory arrays. Programmable memory test algorithms may be invoked by the system user. A factory interface to the BIST facility is provided through boundary scam.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122399940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519776
S. Athan, D. Keezer, J. McKinley
The majority of wafer-level testing of digital devices is condiicted at frequencies below about 10 MHz. This is often ifhe case even when the IC is expected to operate at many times that rate in a system environment. To some extent, low frequency wafer probing can be supplemented by high frequency testing of the packaged device. However, the increased use of multi-chip packaging techniques makes at-speed wafer or die testing mandatory for many applications. Power supply decoupling is critical at fre
{"title":"HIGH FREQUENCY WAFER PROBING AND POWER SUPPLY RESONANCE EFFECTS","authors":"S. Athan, D. Keezer, J. McKinley","doi":"10.1109/TEST.1991.519776","DOIUrl":"https://doi.org/10.1109/TEST.1991.519776","url":null,"abstract":"The majority of wafer-level testing of digital devices is condiicted at frequencies below about 10 MHz. This is often ifhe case even when the IC is expected to operate at many times that rate in a system environment. To some extent, low frequency wafer probing can be supplemented by high frequency testing of the packaged device. However, the increased use of multi-chip packaging techniques makes at-speed wafer or die testing mandatory for many applications. Power supply decoupling is critical at fre<quencies above about SoMHz and proper techniques are typically frequency dependant. In this paper we retiew the oplions available for such tests at frequencies in the range of several hundred MegaHertz for high pincount devices (40 to 100 or more pins) and multiple GigaHertz for low-tomoderate pincounts[l-I0]. A circuit model is described whlich predicts the noise effects in high frequency wafer probing.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117038621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519794
P. Maxwell
From the perspective of manufacturing environments, the production of integrated circuits is unique, and presents significant challenges. The fundamental problem is that the process by which these ICs are made introduces so many defects into the part being manufactured that we are lucky if we get as many as half of the produced parts being defect-free. For large, complex chips the situation is considerably worse.
{"title":"THE INTERACTION OF TEST AND QUALITY","authors":"P. Maxwell","doi":"10.1109/TEST.1991.519794","DOIUrl":"https://doi.org/10.1109/TEST.1991.519794","url":null,"abstract":"From the perspective of manufacturing environments, the production of integrated circuits is unique, and presents significant challenges. The fundamental problem is that the process by which these ICs are made introduces so many defects into the part being manufactured that we are lucky if we get as many as half of the produced parts being defect-free. For large, complex chips the situation is considerably worse.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129268631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519727
K. Wagner, T. Williams
Board test using functioiial self-test code can be augmented by concurrently sampling signals at chip boundaries, compressing this data, and verifying its signature in-line in the code. This is a general method to enhance board test and diagnosis, po1,erXtidy adding every chip J/O pin as an observation point that is observed frequently and coupled to the self-test. Tests continue to execute at the normal board operating speed. This combination of fnnctional and strudural testing offers improved effectiveness over functional testing alone.
{"title":"ENHANCING BOARD FUNCTIONAL SELF-TEST BY CONCURRENT SAMPLING","authors":"K. Wagner, T. Williams","doi":"10.1109/TEST.1991.519727","DOIUrl":"https://doi.org/10.1109/TEST.1991.519727","url":null,"abstract":"Board test using functioiial self-test code can be augmented by concurrently sampling signals at chip boundaries, compressing this data, and verifying its signature in-line in the code. This is a general method to enhance board test and diagnosis, po1,erXtidy adding every chip J/O pin as an observation point that is observed frequently and coupled to the self-test. Tests continue to execute at the normal board operating speed. This combination of fnnctional and strudural testing offers improved effectiveness over functional testing alone.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124544758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519518
Bong-Hee Park, P. R. Menon
In this paper, two methods of applying two-pattern tests for stuck-open faults in scan-testable CMOS sequential circuits are presented. These methods require shifting in only one pattern and require no special latches in the scan chain. Sufficient conditions for 110bust testability of all single FET stuck-open faults and design techniques for robustly scan-testable CMOS sequential circuits are presented. These techniques lead to realizations with at most two additional inputs and some additional FETS in the first-level gates.
{"title":"ROBUSTLY SCAN-TESTABLE CMOS SEQUENTIAL CIRCUITS","authors":"Bong-Hee Park, P. R. Menon","doi":"10.1109/TEST.1991.519518","DOIUrl":"https://doi.org/10.1109/TEST.1991.519518","url":null,"abstract":"In this paper, two methods of applying two-pattern tests for stuck-open faults in scan-testable CMOS sequential circuits are presented. These methods require shifting in only one pattern and require no special latches in the scan chain. Sufficient conditions for 110bust testability of all single FET stuck-open faults and design techniques for robustly scan-testable CMOS sequential circuits are presented. These techniques lead to realizations with at most two additional inputs and some additional FETS in the first-level gates.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123401408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519694
E. Weis, E. Kinsbron, M. Snyder, B. Vogel, N. Croitoru
As an outcome of the advances in integrated circuit fabrication technology, Electromigration has become a major reliability conceriz in silicon VLSI circuits. This paper present an innovative testing approach that has been implemented and allows a substantial reduction in the Electromigration test times of V LSI metal thin films. The scope and the detail of Electromigration test structures and various Electromigration test signals are emphasized. The impact of the slew rate of the testing signal upon the Electromigration resis- tance of the VLSI conductor is analyzed. Embed- ded statistical analysis techniques that have been applied enable to correlate the most valuable high accelerated Electromigration lifetime tests to real li fetime Electromigration performance of thin conductors within VLSI.
{"title":"ELECTROMIGRATION EFFECTS IN VLSI DUE TO VARIOUS CURRENT TYPES","authors":"E. Weis, E. Kinsbron, M. Snyder, B. Vogel, N. Croitoru","doi":"10.1109/TEST.1991.519694","DOIUrl":"https://doi.org/10.1109/TEST.1991.519694","url":null,"abstract":"As an outcome of the advances in integrated circuit fabrication technology, Electromigration has become a major reliability conceriz in silicon VLSI circuits. This paper present an innovative testing approach that has been implemented and allows a substantial reduction in the Electromigration test times of V LSI metal thin films. The scope and the detail of Electromigration test structures and various Electromigration test signals are emphasized. The impact of the slew rate of the testing signal upon the Electromigration resis- tance of the VLSI conductor is analyzed. Embed- ded statistical analysis techniques that have been applied enable to correlate the most valuable high accelerated Electromigration lifetime tests to real li fetime Electromigration performance of thin conductors within VLSI.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134239338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519737
J. Savir, R. Berry
In many circles at-speed test is synonymous to AC test. The object of this paper is to root out this misconception. In order to achieve an effective AC test special attention must be paid to the way the patterns are generated. The AC strength is a measure that allows assessing how well a pattern generator can serve in applying AC test vectors to the logic. Generators with high AC strengths tend to perform better than generators with low AC strengths.
{"title":"AT-SPEED TEST IS NOT NECESSARILY AN AC TEST","authors":"J. Savir, R. Berry","doi":"10.1109/TEST.1991.519737","DOIUrl":"https://doi.org/10.1109/TEST.1991.519737","url":null,"abstract":"In many circles at-speed test is synonymous to AC test. The object of this paper is to root out this misconception. In order to achieve an effective AC test special attention must be paid to the way the patterns are generated. The AC strength is a measure that allows assessing how well a pattern generator can serve in applying AC test vectors to the logic. Generators with high AC strengths tend to perform better than generators with low AC strengths.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134569562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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