F. Clermidy, C. Bernard, R. Lemaire, Jérôme Martin, I. Miro-Panadès, Y. Thonnart, P. Vivet, N. Wehn
{"title":"MAGALI: A Network-on-Chip based multi-core system-on-chip for MIMO 4G SDR","authors":"F. Clermidy, C. Bernard, R. Lemaire, Jérôme Martin, I. Miro-Panadès, Y. Thonnart, P. Vivet, N. Wehn","doi":"10.1109/ICICDT.2010.5510291","DOIUrl":null,"url":null,"abstract":"Chips for digital baseband processing have long been based on simple fixed pipeline structures connecting processing elements. The emergence of complex multi-modes applications like 3GPP-LTE, Software Defined Radio or Cognitive Radio leads to fast handover need between Telecommunication protocols. On one hand, to fulfill these new requirements, more flexible architectures are required. On the other hand, such applications demand more computing performance, and thus power consumption is a concern. In this paper, we present a new chip dedicated to baseband processing. Based on an asynchronous Network-on-Chip and 23 processing units, it delivers 37 GOPS of peak performance. A dynamic reconfiguration management is deployed on the chip for fast handover between modes, with less than 50 µs of full reconfiguration. The asynchronous Network-on-Chip used to communicate allows a complete frequency decoupling between the units. A distributed power management strategy leads to less than 500 mW power consumption in typical use.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"23","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Conference on Integrated Circuit Design and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2010.5510291","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 23
Abstract
Chips for digital baseband processing have long been based on simple fixed pipeline structures connecting processing elements. The emergence of complex multi-modes applications like 3GPP-LTE, Software Defined Radio or Cognitive Radio leads to fast handover need between Telecommunication protocols. On one hand, to fulfill these new requirements, more flexible architectures are required. On the other hand, such applications demand more computing performance, and thus power consumption is a concern. In this paper, we present a new chip dedicated to baseband processing. Based on an asynchronous Network-on-Chip and 23 processing units, it delivers 37 GOPS of peak performance. A dynamic reconfiguration management is deployed on the chip for fast handover between modes, with less than 50 µs of full reconfiguration. The asynchronous Network-on-Chip used to communicate allows a complete frequency decoupling between the units. A distributed power management strategy leads to less than 500 mW power consumption in typical use.