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2010 IEEE International Conference on Integrated Circuit Design and Technology最新文献

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Novel SER standards: Backgrounds and methodologies 新的SER标准:背景和方法
Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510259
E. Ibe, K. Shimbo, Tadanobu Toba, Yoshio Taniguchi, H. Taniguchi
Standard methods to quantify SER susceptibility in memory devices have been established during 2000–2008. JESD89A issued in 2006 covers a wide variety of test methods for terrestrial neutrons and alpha particles. Spallation and (quasi-) monoenergetic neutron tests are among the best options for the SER tests. The methods, however, are being recognized as getting more inaccurate as device scaling proceeds. SER in logic devices is also getting more serious so that standard testing methods have to be established for logic devices. The new standards may include strategies for mitigation of SERs as well. The backgrounds and methodologies to promote new SER standards for device, chip, board layers are discussed in the present paper.
在2000-2008年期间,已经建立了量化存储器件中SER磁化率的标准方法。2006年发布的JESD89A涵盖了地球中子和α粒子的各种测试方法。散裂和(准)单能中子试验是SER试验的最佳选择。然而,随着设备规模的扩大,这些方法被认为越来越不准确。逻辑器件中的SER问题也日益严重,必须建立标准的测试方法。新标准可能还包括减轻SERs的战略。本文讨论了推动器件层、芯片层、板层的新SER标准的背景和方法。
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引用次数: 6
Dynamic biasing techniques for RF power amplifier linearity and efficiency improvement 动态偏置技术对射频功率放大器线性度和效率的改善
Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510253
N. Deltimple, L. Leyssenne, E. Kerhervé, Y. Deval, D. Belot
Nowadays, mobile handsets have to deal with several challenges. First of all, a good efficiency is essential in order to save power and battery life-time. Then, to cater to multi-standards operation which provide very high data rates, strong linearity performances are mandatory, to the expense of transmit front-end efficiency. As RF Power Amplifiers (PAs) are the most power consuming components, this paper describes an approach of managing the efficiency-linearity trade-off by using dynamic biasing. The dynamic biasing allows a power control of the PA and is brought into play both with an open-loop solution and a closed-loop solution. The main purpose of the paper is to present a description of the circuits developed and their performances in terms of output power, linearity and efficiency. The reconfigurable PAs are dedicated to UMTS-WCDMA and WiFi/WiMAX standards.
如今,手机必须应对几个挑战。首先,为了节省电力和电池寿命,良好的效率是必不可少的。然后,为了满足提供非常高的数据速率的多标准操作,必须具有强的线性性能,以牺牲传输前端效率为代价。由于射频功率放大器(pa)是最耗电的元件,本文描述了一种利用动态偏置来管理效率-线性度权衡的方法。动态偏置允许对PA进行功率控制,并通过开环解决方案和闭环解决方案发挥作用。本文的主要目的是介绍所开发的电路及其在输出功率,线性度和效率方面的性能。可重构的pa专用于UMTS-WCDMA和WiFi/WiMAX标准。
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引用次数: 10
Low power technology/circuit co-development for advanced mobile devices 先进移动设备的低功耗技术/电路联合开发
Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510260
G. Yeap
Technology options at 45nm and 32/28nm have been optimized for various mobile device applications. Disposable high performance technology is introduced to satisfy both high speed and low power requirement of modern convergence mobile computing and communication device. Dual Core Oxide scheme using SiON/Poly gate stack was used in 45nm. Scaled SiON/Poly gate stack is sufficient for 32/28nm low power/low cost technology, while HK/MG gate stack with strong process induced stress option is needed for high performance technology.
45nm和32/28nm的技术选项已针对各种移动设备应用进行了优化。为满足现代融合移动计算和通信设备的高速和低功耗要求,引入了一次性高性能技术。在45nm采用了采用硅/聚栅极叠加的双核氧化方案。对于32/28nm低功耗/低成本技术来说,缩放的硅/聚栅极堆栈是足够的,而对于高性能技术来说,需要具有强工艺诱导应力选项的HK/MG栅极堆栈。
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引用次数: 0
High-speed links for memory interface 存储器接口的高速链路
Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510752
J. Sim, Seon-Kyoo Lee, Young-Sik Kim, Y. Sohn, Joo-Sun Choi
Memory, as a fundamental component of a system, has been a leading drive for high-speed parallel links, and it requires interface technology providing stable data rate of multi-Gb/s/pin. The highest data rate in memory IO, presented by GDDR5, shows the data rate of up to 6Gb/s/pin with the traditional single-ended signaling on PCB. Further step to higher throughput, however, presents critical problems which must be overcome by taking challenges in packaging, process as well as circuit design. This paper reviews current status of memory interface circuits and introduces several promising interface technologies such as TSV, Wide-IO, inductive coupling, and multiple serial links.
存储器作为系统的基本组成部分,一直是高速并行链路的主要驱动力,它要求接口技术提供稳定的多gb /s/pin的数据速率。内存IO中数据速率最高的是GDDR5,采用传统的PCB单端信令,数据速率高达6Gb/s/pin。然而,进一步提高吞吐量提出了关键问题,必须通过在封装,工艺和电路设计方面的挑战来克服这些问题。本文综述了存储接口电路的现状,介绍了TSV、Wide-IO、电感耦合和多串行链路等几种有前途的接口技术。
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引用次数: 3
Fast Monte Carlo method via reduced sample number and node filtering 快速蒙特卡罗方法通过减少样本数量和节点滤波
Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510272
Inhak Han, Lee-eun Yu, Youngsoo Shin
Monte Carlo (MC) method is convenient and robust to estimate timing yield of circuits under the influence of process variations. The important question in MC method is the number of samples while we assure a desired accuracy of yield estimate, which is often addressed using a rule of thumb. Minimum number of samples can be estimated via approximation by a normal distribution, but the provided number may be too small to be used in practice considering that target yield, which is used to derive the number, is unknown. Chebyshev's inequality has been used to derive a sample number, but the number is too large this time. We develop a new expression, which provides the sample number that is much closer to the minimum (3× to 8×) compared to the number provided by Chebyshev's inequality (5× to 15×). We also propose a simple node filtering algorithm, where we identify the nodes that are likely to affect timing yield; the simulation with each MC sample can handle only a fraction of circuit elements as a result. Reducing the number of MC samples and simulating only selected nodes together yield 27× to 125× speedup over standard MC method.
蒙特卡罗(MC)方法对于过程变化影响下的电路时序良率估计具有方便和鲁棒性。在MC方法中,重要的问题是样品的数量,同时我们保证期望的产量估计的准确性,这通常是使用经验法则来解决的。最小样本数量可以通过正态分布的近似估计,但考虑到用于推导样本数量的目标产量未知,所提供的样本数量可能太小而无法在实践中使用。切比雪夫不等式已经被用来推导一个样本数,但是这次的样本数太大了。我们开发了一个新的表达式,它提供了更接近最小值(3x到8x)的样本数,而不是由切比雪夫不等式(5x到15x)提供的样本数。我们还提出了一种简单的节点过滤算法,其中我们识别可能影响时序产量的节点;因此,每个MC样本的模拟只能处理一小部分电路元件。减少MC样本数量并只模拟选定的节点,与标准MC方法相比,速度提高了27到125倍。
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引用次数: 0
Narrowing the margins with elastic clocks 用弹性时钟缩小边缘
Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510273
J. Cortadella, L. Lavagno, Djavad Amiri, J. Casanova, C. Macián, F. Martorell, Juan A. Moya, L. Necchi, D. Sokolov, E. Tuncer
The continuous shrinking of process geometries increases variability and demands for conservative margins that have a negative impact on performance. With conventional clocks, the cycle period has to be defined to accommodate the worst-case variations during the lifetime of the circuit. Elastic Clocks arise as a new paradigm to reduce the margins without sacrificing robustness. Their cycle-by-cycle adaptation to static and dynamic variability enables the use of reduced margins that only need to cover the differential variability of the circuit delays with regard to the elastic period. Given the substantial spatio-temporal correlation within every die, a significant reduction in the margins required to cover process variability, voltage and temperature fluctuations and aging can be achieved.
工艺几何形状的不断缩小增加了可变性和对保守边际的需求,这对性能产生了负面影响。对于传统时钟,必须定义周期以适应电路生命周期内最坏情况的变化。弹性时钟作为一种新的范例出现,在不牺牲鲁棒性的情况下减少了余量。它们对静态和动态可变性的逐周期适应使得只需要覆盖有关弹性周期的电路延迟的微分可变性的减少余量得以使用。考虑到每个模具内的大量时空相关性,可以实现覆盖工艺变异性,电压和温度波动以及老化所需的裕度的显着减少。
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引用次数: 16
Progress and challenges of tungsten-filled through-silicon via 填钨硅通孔的研究进展与挑战
Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510274
D. Triyoso, T. Dao, T. Kropewnicki, F. Martínez, R. Noble, M. Hamilton
Through Silicon Via (TSV) has been used for back-end packaging and more recently, for front end active device integration. In this work we report recent progress and challenges for via cleaning, via filling and wafer bow / stress monitoring. Furthermore, the importance of preparation technique for accurate characterization of tungsten-filled TSV profile will be presented.
通过硅通孔(TSV)已用于后端封装和最近的前端有源器件集成。在这项工作中,我们报告了通过清洗,通过填充和晶圆弯曲/应力监测的最新进展和挑战。此外,还指出了制备技术对准确表征钨填充TSV轮廓的重要性。
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引用次数: 9
Simplified parameter extraction method for modeling on-chip spiral inductors 片上螺旋电感器建模的简化参数提取方法
Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510247
E. L. Tan, W. Koh
This paper presents a simplified parameter extraction method for modeling on-chip spiral inductors. Our method bypasses time-consuming numerical optimization and is simpler than previous parameter extraction procedure. The parameters of the spiral inductor model can be extracted simply and directly without involving complicated formulas. It is also found that the extracted parameters are more accurate especially in the substrate lateral coupling elements. The extracted model shows excellent agreement between simulation and measurement over the frequency range of interest. With its simplicity and accuracy, the simplified parameter extraction method herein will find usefulness in the modeling and design of spiral inductors for radio frequency integrated circuits.
提出了一种简化的片上螺旋电感建模参数提取方法。该方法省去了耗时的数值优化,比以往的参数提取过程更简单。螺旋电感器模型参数的提取方法简单直接,不需要复杂的公式。同时发现,所提取的参数更精确,特别是在基底横向耦合单元中。在感兴趣的频率范围内,提取的模型在仿真和测量之间表现出良好的一致性。本文提出的简化参数提取方法简单、准确,可用于射频集成电路中螺旋电感的建模和设计。
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引用次数: 0
A GPU/CUDA implementation of the collection-diffusion model to compute SER of large area and complex circuits 一种用于计算大面积复杂电路SER的采集-扩散模型的GPU/CUDA实现
Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510293
J. Autran, S. Uznanski, S. Martinie, P. Roche, G. Gasiot, D. Munteanu
This work reports the CUDA implementation of the collection-diffusion model to compute the soft-error rate (SER) of large area and/or complex circuits on graphics processing units (GPU). We detail the time parallelization introduced in the algorithm to accelerate by one order of magnitude the SER calculation. Code performances are evaluated on a NVIDIA Tesla C1060 GPU card for the calculation of the SER of a 65nm SRAM circuit subjected to an alpha-particle source irradiation.
本工作报告了收集-扩散模型的CUDA实现,用于计算图形处理单元(GPU)上大面积和/或复杂电路的软错误率(SER)。我们详细介绍了算法中引入的时间并行化,以加速一个数量级的SER计算。在NVIDIA Tesla C1060 GPU卡上对代码性能进行了评估,计算了α粒子源辐照下65nm SRAM电路的SER。
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引用次数: 7
Overlay-aware interconnect yield modeling in double patterning lithography 双图版光刻中覆盖感知互连良率建模
Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510275
Minoo Mirsaeedi, M. Anis
In double patterning lithography, overlay error between two patterning steps at the same layer results in critical dimensions variability. In order to optimize the yield loss due to overlay error, statistical design techniques should be applied since overlay error is segueing from a systematic error into a random one for technology nodes smaller than 45-nm. In this paper, the effects of overlay error on interconnect layers are studied and the interconnect yield in presence of overlay error is modeled. Next, a yield optimization method is proposed to improve the parametric and functional yields of interconnect layers. Experimental results show that parametric yield loss is more problematic in negativetone DPL. Moreover, we show that different DFM techniques such as wire spreading are necessary to reach design constraints.
在双图案化光刻中,同一层上两个图案化步骤之间的叠加误差导致临界尺寸变化。为了优化由于覆盖误差造成的良率损失,应该应用统计设计技术,因为覆盖误差从系统误差转变为小于45 nm的技术节点的随机误差。本文研究了叠加误差对互连层数的影响,建立了存在叠加误差时的互连成品率模型。其次,提出了一种良率优化方法,以提高互连层的参数和函数良率。实验结果表明,参数良率损失在负调DPL中更为严重。此外,我们证明了不同的DFM技术,如导线扩展是达到设计约束所必需的。
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引用次数: 1
期刊
2010 IEEE International Conference on Integrated Circuit Design and Technology
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