Power switch optimization and sizing in 65nm PD-SOI considering supply voltage noise

Abstract

In this paper, several power gating solutions are analysed in 65nm PDSOI technology, taking into account the implementation area. A new figure of merit has been proposed to easily determine the best tradeoff between leakage, drive current and area. It shows that the best solution is to use a Body-Contacted transistor with a non-minimal gate length, enabling leakage currents of the same order of magnitude than in Bulk. A second analysis on specific PD-SOI Logic CORE electrical behaviour has been performed. This analysis allows determining the power switch network sizing implementation taking into account decoupling capacitance, ON Logic CORE current and equivalent parasitic supply inductance.