Area I/O flip-chip packaging to minimize interconnect length

Abstract

This paper discusses an approach using area interconnect to achieve high performance for an experimental multichip microprocessor. The described method is being used in the PUMA project at the University of Michigan to design a processor that has a clock speed goal of 1 GHz. The approach relies on the coordinated placement of functional blocks on chips, and the resulting chips on the MCM. The use of area array pads to provide high bandwidth interconnections between the chips, and low inductance power connection to the MCM is also essential. Three stages of MCM development for the project are described.