Pub Date : 1997-02-04DOI: 10.1109/MCMC.1997.569348
A. J. Przekwas, Y. Jiang, Z. Tan
A novel computational approach, VPE, has been presented for multi-scale analysis of electronics packaging/cooling. The VPE software system has been designed for fully automated model assembly, grid generation based on compact, reusable electronic component database representation, interactive design, and visualization. Advanced thermal analysis code, CFD-ACE, has been developed with unstructured, solution adaptive grid. The paper has demonstrated a novel concept of unstructured solution adaptive grids for high resolution flow and thermal analysis of electronics components and boards. It was demonstrated on detailed 3D heat transfer studies of MCMs and their assemblies. It has also been demonstrated that a high fidellity multi-scale thermal analysis is possible in which 3D air flow/heat transfer is solved simultaneously with detailed heat condition within individual electronics components. At present, the VPE is being extended for fully automatic design starting from the geometry definition up to the visualization step. A thermal stress module is being linked for full thermo-mechanical analysis.
{"title":"Multiscale thermal design of MCMs with high resolution unstructured adaptive simulation tools","authors":"A. J. Przekwas, Y. Jiang, Z. Tan","doi":"10.1109/MCMC.1997.569348","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569348","url":null,"abstract":"A novel computational approach, VPE, has been presented for multi-scale analysis of electronics packaging/cooling. The VPE software system has been designed for fully automated model assembly, grid generation based on compact, reusable electronic component database representation, interactive design, and visualization. Advanced thermal analysis code, CFD-ACE, has been developed with unstructured, solution adaptive grid. The paper has demonstrated a novel concept of unstructured solution adaptive grids for high resolution flow and thermal analysis of electronics components and boards. It was demonstrated on detailed 3D heat transfer studies of MCMs and their assemblies. It has also been demonstrated that a high fidellity multi-scale thermal analysis is possible in which 3D air flow/heat transfer is solved simultaneously with detailed heat condition within individual electronics components. At present, the VPE is being extended for fully automatic design starting from the geometry definition up to the visualization step. A thermal stress module is being linked for full thermo-mechanical analysis.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114999687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-02-04DOI: 10.1109/MCMC.1997.569347
A. Madni, C. C. Madni
Multichip Module (MCM) design is a complex process that requires multiple tradeoffs and design iterations. It involves multiple core competencies that seldom reside in a single organization or geographical site. It typically requires multiple design tools that come from different vendors. Design process management in such an environment is key to infusing discipline as well as reducing design cycle time. This paper presents an innovative CORBA 2.0-compliant Internet/WWW-based wide-area design process management approach that is based on dynamically constructed "flows". At the heart of the design process manager is an object-oriented meta-model of the design process. This model captures and inter-relates all key design objects that are required to manage and improve the MCM design process. A key aspect of the design process manager is its multi-perspective visualization capability that allows both managers and designers to view the MCM design process from their respective perspectives.
{"title":"An adaptive wide-area design process manager for collaborative multichip module design","authors":"A. Madni, C. C. Madni","doi":"10.1109/MCMC.1997.569347","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569347","url":null,"abstract":"Multichip Module (MCM) design is a complex process that requires multiple tradeoffs and design iterations. It involves multiple core competencies that seldom reside in a single organization or geographical site. It typically requires multiple design tools that come from different vendors. Design process management in such an environment is key to infusing discipline as well as reducing design cycle time. This paper presents an innovative CORBA 2.0-compliant Internet/WWW-based wide-area design process management approach that is based on dynamically constructed \"flows\". At the heart of the design process manager is an object-oriented meta-model of the design process. This model captures and inter-relates all key design objects that are required to manage and improve the MCM design process. A key aspect of the design process manager is its multi-perspective visualization capability that allows both managers and designers to view the MCM design process from their respective perspectives.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125040923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-02-04DOI: 10.1109/MCMC.1997.569345
S.J. Yang, T. Chang, Ruey-Wen Chien, E. Wang, T. Gabara, K. Tai, R. Frye
It is well known that a bare die packaged in a MCM module will be exposed to a better electrical environment. Besides speed improvement, due to the lighter loading effects, chip power consumption can be reduced if conventional CMOS I/O buffers are replaced by some smaller and fancier ones, in which ESD protection mechanisms are removed. In this approach, chip designer must be involved in the task for devising those target chips to be packed into a MCM. In this paper, three types of differential CMOS I/O buffers especially for MCM will be discussed and their performances compared. In addition to the differential types, a new sets of I/O buffers, switchable MCM CMOS I/Os, meeting both MCM and PWB requirements, will also be investigated. And finally, the simulation and experiment results will follow.
{"title":"High speed I/O buffer design for MCM","authors":"S.J. Yang, T. Chang, Ruey-Wen Chien, E. Wang, T. Gabara, K. Tai, R. Frye","doi":"10.1109/MCMC.1997.569345","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569345","url":null,"abstract":"It is well known that a bare die packaged in a MCM module will be exposed to a better electrical environment. Besides speed improvement, due to the lighter loading effects, chip power consumption can be reduced if conventional CMOS I/O buffers are replaced by some smaller and fancier ones, in which ESD protection mechanisms are removed. In this approach, chip designer must be involved in the task for devising those target chips to be packed into a MCM. In this paper, three types of differential CMOS I/O buffers especially for MCM will be discussed and their performances compared. In addition to the differential types, a new sets of I/O buffers, switchable MCM CMOS I/Os, meeting both MCM and PWB requirements, will also be investigated. And finally, the simulation and experiment results will follow.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116078334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-02-04DOI: 10.1109/MCMC.1997.569363
F. Kiamilev, A. Krishnamoorthy, R. Rozier, J. Rieve, G. Aplin, C. Hull, R. Farbarik, R. Oettel
Hybrid integration of optoelectronic devices, such as GaAs MQW modulators, to CMOS VLSI circuits provides the opportunity to design ICs that integrate millions of transistors and thousands of high-speed optical I/Os for high-performance computing and switching applications. One of the challenges in designing such large-scale ICs lies in the development of an efficient method for integrating existing VLSI circuit layouts with two-dimensional arrays of optoelectronic devices. This paper presents several such methods and describes their application.
{"title":"Design of ICs for flip-chip integration with optoelectronic device arrays","authors":"F. Kiamilev, A. Krishnamoorthy, R. Rozier, J. Rieve, G. Aplin, C. Hull, R. Farbarik, R. Oettel","doi":"10.1109/MCMC.1997.569363","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569363","url":null,"abstract":"Hybrid integration of optoelectronic devices, such as GaAs MQW modulators, to CMOS VLSI circuits provides the opportunity to design ICs that integrate millions of transistors and thousands of high-speed optical I/Os for high-performance computing and switching applications. One of the challenges in designing such large-scale ICs lies in the development of an efficient method for integrating existing VLSI circuit layouts with two-dimensional arrays of optoelectronic devices. This paper presents several such methods and describes their application.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121365349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-02-04DOI: 10.1109/MCMC.1997.569338
P. Dehkordi, K. Ramamurthi, D. Bouldin, H. Davidson
Microelectronics system designers need to understand and evaluate the impact of advanced packaging parameters which have become an integral part of microelectronics systems. This paper evaluates the impact of bond pitch for a flipchip multichip system through a case study. The SUN MicroSparc CPU was used as a representative of a large design where the design has to be partitioned and interconnected using MCM technology. Early analysis techniques were used to analyze the design for various pitches ranging from 150 to 400 micron in 50 micron increments. Results suggest that various bond pitches affect the system cost/performance and there is a minimum pitch at which lowering the pitch will degrade the cost/performance metrics.
{"title":"Determination of area-array bond pitch for optimum MCM systems: a case study","authors":"P. Dehkordi, K. Ramamurthi, D. Bouldin, H. Davidson","doi":"10.1109/MCMC.1997.569338","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569338","url":null,"abstract":"Microelectronics system designers need to understand and evaluate the impact of advanced packaging parameters which have become an integral part of microelectronics systems. This paper evaluates the impact of bond pitch for a flipchip multichip system through a case study. The SUN MicroSparc CPU was used as a representative of a large design where the design has to be partitioned and interconnected using MCM technology. Early analysis techniques were used to analyze the design for various pitches ranging from 150 to 400 micron in 50 micron increments. Results suggest that various bond pitches affect the system cost/performance and there is a minimum pitch at which lowering the pitch will degrade the cost/performance metrics.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125575868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-02-04DOI: 10.1109/MCMC.1997.569357
I. Yee, R. Miracky, J. Reed, B. Lunceford, Minchuan Wang, D. Cobb, G. Caldwell
A quick-turn flexible process for designing, verifying, and manufacturing multichip modules for use with flip chip ICs was developed. The process starts with MCC's prefabricated customizable substrates. Laser based cut and link processes are used to program the necessary wires on the substrate. Laser direct write is also used to redistribute the flip chip area array bond pads to match the bond pads on the substrate. An efficient design to manufacturing process is assisted with the use of a software tool that allows the user to place and route the interconnections, and prepares the information needed for fabrication of the multichip modules.
{"title":"Flexible manufacturing of multichip modules for flip chip ICs","authors":"I. Yee, R. Miracky, J. Reed, B. Lunceford, Minchuan Wang, D. Cobb, G. Caldwell","doi":"10.1109/MCMC.1997.569357","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569357","url":null,"abstract":"A quick-turn flexible process for designing, verifying, and manufacturing multichip modules for use with flip chip ICs was developed. The process starts with MCC's prefabricated customizable substrates. Laser based cut and link processes are used to program the necessary wires on the substrate. Laser direct write is also used to redistribute the flip chip area array bond pads to match the bond pads on the substrate. An efficient design to manufacturing process is assisted with the use of a software tool that allows the user to place and route the interconnections, and prepares the information needed for fabrication of the multichip modules.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129846157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-02-04DOI: 10.1109/MCMC.1997.569350
Dongsheng Wang, E. Kuh
In high-performance multilayer routing, time delay is an important performance issue which has not been appropriately addressed by previous multilayer routing approaches. This paper proposes a new timing-driven MCM/IC multilayer routing algorithm, named MLR, considering the Elmore delay as well as some other fundamental performance issues, such as the number of layers, vias and the total wirelength. Algorithm MLR assigns all the nets into the routing layers layer-pair by layer-pair based on the layer assignment algorithm. During each pair-layer routing, the timing-driven Steiner area routing algorithm SOAR is used to generate a Steiner tree for each net while minimizing the Elmore delay of the net. For two nodes to be connected for the net being routed, an optimal path from one node to the other is created by the (/spl alpha/,/spl beta/)* algorithm. Additionally, when power and ground nets are considered, some signal nets are routed in the limited routing space on the power and ground layer-pair, which is very useful in decreasing the number of layers needed to complete the routing. The proposed algorithm has been implemented and tested on CBL/NCSU and MCC benchmarks and the experimental results are very promising.
{"title":"A new timing-driven multilayer MCM/IC routing algorithm","authors":"Dongsheng Wang, E. Kuh","doi":"10.1109/MCMC.1997.569350","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569350","url":null,"abstract":"In high-performance multilayer routing, time delay is an important performance issue which has not been appropriately addressed by previous multilayer routing approaches. This paper proposes a new timing-driven MCM/IC multilayer routing algorithm, named MLR, considering the Elmore delay as well as some other fundamental performance issues, such as the number of layers, vias and the total wirelength. Algorithm MLR assigns all the nets into the routing layers layer-pair by layer-pair based on the layer assignment algorithm. During each pair-layer routing, the timing-driven Steiner area routing algorithm SOAR is used to generate a Steiner tree for each net while minimizing the Elmore delay of the net. For two nodes to be connected for the net being routed, an optimal path from one node to the other is created by the (/spl alpha/,/spl beta/)* algorithm. Additionally, when power and ground nets are considered, some signal nets are routed in the limited routing space on the power and ground layer-pair, which is very useful in decreasing the number of layers needed to complete the routing. The proposed algorithm has been implemented and tested on CBL/NCSU and MCC benchmarks and the experimental results are very promising.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128463646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-02-04DOI: 10.1109/MCMC.1997.569354
A. Veluswami, M. Nakhla, Qi-jun Zhang
In this paper, artificial neural networks are applied to the modeling of the frequency-dependent parameters of lossy interconnects. Neural networks are an efficient mathematical tool capable of mapping the relationship between the physical parameters of interconnects and their per-unit-length parameters over a large range of frequency. They offer high on-line speed and are ideally suited for use in iterative computer-aided design and optimization techniques.
{"title":"Modeling the frequency-dependent parameters of high-speed interconnects: a neural network approach","authors":"A. Veluswami, M. Nakhla, Qi-jun Zhang","doi":"10.1109/MCMC.1997.569354","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569354","url":null,"abstract":"In this paper, artificial neural networks are applied to the modeling of the frequency-dependent parameters of lossy interconnects. Neural networks are an efficient mathematical tool capable of mapping the relationship between the physical parameters of interconnects and their per-unit-length parameters over a large range of frequency. They offer high on-line speed and are ideally suited for use in iterative computer-aided design and optimization techniques.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115287460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-02-04DOI: 10.1109/MCMC.1997.569339
T. Schaffer, A. Glaser, S. Rao, P. Franzon
We describe a flip-chip MCM-D implementation of a Data Encryption Standard (DES) engine. Novel features include the following: use of dense area-array I/O to achieve high bandwidth, fully-pipelined architecture which supports multiple encryptions (e.g., triple DES) with no loss of throughput; ability to multiplex datastreams, each under the control of a potentially unique key, and use of the MCM-D substrate to distribute power, ground and clock signals. The chip is being fabricated in a 0.6 /spl mu/m CMOS process, while the MCM is being built in a 4-layer polyimide MCM-D process. Circuit simulations indicate the device will operate with a throughput of 9.6 Gb/s.
我们描述了一个数据加密标准(DES)引擎的倒装芯片MCM-D实现。新颖的功能包括:使用密集的区域阵列I/O来实现高带宽，全流水线架构，支持多种加密(例如，三重DES)，而不会损失吞吐量;能够复用数据流，每个数据流都在一个可能唯一的键的控制下，并使用MCM-D基板来分配电源、接地和时钟信号。该芯片采用0.6 /spl μ m CMOS工艺制造，而MCM采用4层聚酰亚胺MCM- d工艺制造。电路仿真表明，该器件将以9.6 Gb/s的吞吐量运行。
{"title":"A flip-chip implementation of the Data Encryption Standard (DES)","authors":"T. Schaffer, A. Glaser, S. Rao, P. Franzon","doi":"10.1109/MCMC.1997.569339","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569339","url":null,"abstract":"We describe a flip-chip MCM-D implementation of a Data Encryption Standard (DES) engine. Novel features include the following: use of dense area-array I/O to achieve high bandwidth, fully-pipelined architecture which supports multiple encryptions (e.g., triple DES) with no loss of throughput; ability to multiplex datastreams, each under the control of a potentially unique key, and use of the MCM-D substrate to distribute power, ground and clock signals. The chip is being fabricated in a 0.6 /spl mu/m CMOS process, while the MCM is being built in a 4-layer polyimide MCM-D process. Circuit simulations indicate the device will operate with a throughput of 9.6 Gb/s.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125715841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-02-04DOI: 10.1109/MCMC.1997.569351
Xiao-hong Jiang, K. Wu, W. Hong, W. Dai
In this paper, the method of lines (MoL) is used to compute the 2-D and 3-D capacitance matrices of multiconductor interconnects with finite metalization thickness that are embedded in conformal multilayered dielectric media. Results show a good agreement with the published data. By contrast, this technique has efficient calculation and flexible handling of conductors having arbitrarily shaped topology.
{"title":"Fast extraction of the capacitance matrix of multilayered multiconductor interconnects using the method of lines","authors":"Xiao-hong Jiang, K. Wu, W. Hong, W. Dai","doi":"10.1109/MCMC.1997.569351","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569351","url":null,"abstract":"In this paper, the method of lines (MoL) is used to compute the 2-D and 3-D capacitance matrices of multiconductor interconnects with finite metalization thickness that are embedded in conformal multilayered dielectric media. Results show a good agreement with the published data. By contrast, this technique has efficient calculation and flexible handling of conductors having arbitrarily shaped topology.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133847147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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