Power-aware test pattern generation for improved concurrency at the core level

Abstract

A functional automatic test pattern generation (ATPG) for embedded core testing is presented that meets power constraints requirements and time to market consideration. Quick turnaround time for the ATPG is obtained by utilizing compact sets of test vectors. Use of test functions for the embedded cores control the switching activity so that the generated test vectors meet constraints on power dissipation. Concurrency is guaranteed with the use of test functions (as opposed to patterns) and appropriate I/O pin TAM allocations during a compact ATPG process that benefit from pre-existing test vectors. Low power dissipation is also facilitated by test functions and is driven by a metric that requires that a very small portion of each core net-list is available