V. Mehta, M. Marek-Sadowska, Zhiyuan Wang, Kun-Han Tsai, J. Rajski
With feature sizes steadily shrinking, manufacturing defects and parameter variations often cause design timing failures. It is essential that those errors be correctly and quickly diagnosed. The existing delay-fault diagnosis algorithms cannot identify the delay faults that require nonrobust tests, because they ignore nonrobust propagation conditions while emulating the failure analyzer's behavior. We propose a novel approach to perform delay-fault diagnosis for robust and nonrobust tests. The experimental results show that our approach can diagnose delay faults with good resolution. It is stable with respect to delay variations that the failure analyzer might experience
{"title":"Delay fault diagnosis for nonrobust test","authors":"V. Mehta, M. Marek-Sadowska, Zhiyuan Wang, Kun-Han Tsai, J. Rajski","doi":"10.1109/ISQED.2006.45","DOIUrl":"https://doi.org/10.1109/ISQED.2006.45","url":null,"abstract":"With feature sizes steadily shrinking, manufacturing defects and parameter variations often cause design timing failures. It is essential that those errors be correctly and quickly diagnosed. The existing delay-fault diagnosis algorithms cannot identify the delay faults that require nonrobust tests, because they ignore nonrobust propagation conditions while emulating the failure analyzer's behavior. We propose a novel approach to perform delay-fault diagnosis for robust and nonrobust tests. The experimental results show that our approach can diagnose delay faults with good resolution. It is stable with respect to delay variations that the failure analyzer might experience","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114973317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For statistical timing analysis and physical design optimization, interconnect delay metrics that model the delay as a function of the metal process variations are very important. Accurate linear or at most second order delay models in terms of the process variables are necessary to efficiently propagate uncertainty in the state-of-the-art VLSI designs with millions of transistors and on chip interconnects. In this paper, we develop a method to extend the traditional moment based delay analysis of interconnects to consider the impact of Gaussian metal process variations and obtain mean-square optimal linear delay models for interconnects. We consider linear models for the variations in the conductance and capacitance of interconnects and represent the moments (m0, m1, m2) of the interconnect impulse response as a first order orthogonal polynomial series expansion in the process variables. We obtain the coefficients of the expansion by using the Galerkin residual error minimization method on the recursive equations that relate the interconnect moments (m0, m1 , m2). We compare the accuracy of our approach against SPICE based Monte Carlo simulations and demonstrate a good match
{"title":"Variational interconnect delay metrics for statistical timing analysis","authors":"P. Ghanta, S. Vrudhula","doi":"10.1109/ISQED.2006.143","DOIUrl":"https://doi.org/10.1109/ISQED.2006.143","url":null,"abstract":"For statistical timing analysis and physical design optimization, interconnect delay metrics that model the delay as a function of the metal process variations are very important. Accurate linear or at most second order delay models in terms of the process variables are necessary to efficiently propagate uncertainty in the state-of-the-art VLSI designs with millions of transistors and on chip interconnects. In this paper, we develop a method to extend the traditional moment based delay analysis of interconnects to consider the impact of Gaussian metal process variations and obtain mean-square optimal linear delay models for interconnects. We consider linear models for the variations in the conductance and capacitance of interconnects and represent the moments (m0, m1, m2) of the interconnect impulse response as a first order orthogonal polynomial series expansion in the process variables. We obtain the coefficients of the expansion by using the Galerkin residual error minimization method on the recursive equations that relate the interconnect moments (m0, m1 , m2). We compare the accuracy of our approach against SPICE based Monte Carlo simulations and demonstrate a good match","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123132378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Noise glitches can cause functional errors or failures if they are latched into sequential cells. Thus it is very important to determine or characterize noise failure criteria of sequential cells. However, characterizing noise failure criteria of sequential cells is very computationally expensive because it often requires multiple transient simulations with different clock waveform shapes and alignments, known as clock sweeping. In this paper, we propose a new technique that eliminates the clock sweeping by using the meta-stable point of sequential cells. Our experiments with industrial circuits have shown that the proposed method is on average 58times faster than the conventional clock sweeping method and its average error is only 2.4%
{"title":"Fast sequential cell noise immunity characterization using meta-stable point of feedback loop","authors":"N. Oh, Li Ding, Alireza Kasnavi","doi":"10.1109/ISQED.2006.67","DOIUrl":"https://doi.org/10.1109/ISQED.2006.67","url":null,"abstract":"Noise glitches can cause functional errors or failures if they are latched into sequential cells. Thus it is very important to determine or characterize noise failure criteria of sequential cells. However, characterizing noise failure criteria of sequential cells is very computationally expensive because it often requires multiple transient simulations with different clock waveform shapes and alignments, known as clock sweeping. In this paper, we propose a new technique that eliminates the clock sweeping by using the meta-stable point of sequential cells. Our experiments with industrial circuits have shown that the proposed method is on average 58times faster than the conventional clock sweeping method and its average error is only 2.4%","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"251 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120974120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A framework that relates the size of FPGA reconfiguration data to the number of minterms of a specially constructed function is presented. Three techniques, variable mapping optimization, circuit don't-care modification, and look-up table input permutation, are developed to minimize minterms of the special function. The method to integrate the proposed techniques into FPGA design automation flow is discussed and experimental results are presented
{"title":"Minimizing FPGA reconfiguration data at logic level","authors":"K. Raghuraman, Haibo Wang, S. Tragoudas","doi":"10.1109/ISQED.2006.87","DOIUrl":"https://doi.org/10.1109/ISQED.2006.87","url":null,"abstract":"A framework that relates the size of FPGA reconfiguration data to the number of minterms of a specially constructed function is presented. Three techniques, variable mapping optimization, circuit don't-care modification, and look-up table input permutation, are developed to minimize minterms of the special function. The method to integrate the proposed techniques into FPGA design automation flow is discussed and experimental results are presented","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127197518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Srinivasan, P. Muthana, R. Mandrekar, E. Engin, Jinwoo Choi, M. Swaminathan
Improvements in electrical performance of microelectronic systems can be achieved by the integration of passive elements such as capacitors, resistors and inductors. The advantage of embedded passives is their low parasitic values. In this paper, enhancement of signal-integrity and power-integrity is investigated when a high-k planar capacitor is used as a power-ground plane, with embedded high-k discrete capacitors that have low ESI and ESR values as decoupling capacitors for SSN suppression. In order to capture the effects of embedded capacitor performance, a test-structure involving many signal-lines referenced to a power-ground plane was simulated. Simulation results show that the high-k planar capacitor reduces coupling of noise currents through the power-ground planes and helps improve the eye-opening. Simulation results have been quantified for a case, where a fewer number of embedded discrete capacitors helps reduce SSN more significantly than surface-mounts. Transient co-simulation of the signal delivery network (SDN) and the power-delivery network (PDN) are performed using Y-parameters
{"title":"Enhancement of signal integrity and power integrity with embedded capacitors in high-speed packages","authors":"K. Srinivasan, P. Muthana, R. Mandrekar, E. Engin, Jinwoo Choi, M. Swaminathan","doi":"10.1109/ISQED.2006.60","DOIUrl":"https://doi.org/10.1109/ISQED.2006.60","url":null,"abstract":"Improvements in electrical performance of microelectronic systems can be achieved by the integration of passive elements such as capacitors, resistors and inductors. The advantage of embedded passives is their low parasitic values. In this paper, enhancement of signal-integrity and power-integrity is investigated when a high-k planar capacitor is used as a power-ground plane, with embedded high-k discrete capacitors that have low ESI and ESR values as decoupling capacitors for SSN suppression. In order to capture the effects of embedded capacitor performance, a test-structure involving many signal-lines referenced to a power-ground plane was simulated. Simulation results show that the high-k planar capacitor reduces coupling of noise currents through the power-ground planes and helps improve the eye-opening. Simulation results have been quantified for a case, where a fewer number of embedded discrete capacitors helps reduce SSN more significantly than surface-mounts. Transient co-simulation of the signal delivery network (SDN) and the power-delivery network (PDN) are performed using Y-parameters","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127258126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gate-length biasing is a runtime leakage reduction technique that leverages on the short-channel effect by marginally increasing the gate-length of MOS devices to significantly reduce their leakage current for a small delay penalty. The technique was shown to work effectively with multi-threshold-voltage assignment, the only mainstream approach for runtime leakage reduction. Typically, designers use threshold voltages selected by the foundries to optimize their designs. Higher threshold-voltage devices, that are less leaky but slow, are assigned to non-critical paths and lower threshold-voltage devices, that are fast but leaky, are assigned to critical paths. In this paper we study the effect of modifying threshold voltages set by the foundry on leakage reduction achieved on three large, real-world designs. We assess the impact of the availability of gate-length biasing on threshold voltage selection. We achieve comparable leakage reductions when foundry-set dual threshold voltages are used with biasing than when foundry-set triple threshold voltages are used without biasing. Our results indicate that leakage reductions can be improved if threshold voltages are carefully chosen considering the availability of gate-length biasing. We also observe that foundry-set threshold voltages are not optimal for achieving best possible leakage reductions
{"title":"Impact of gate-length biasing on threshold-voltage selection","authors":"A. Kahng, S. Muddu, P. Sharma","doi":"10.1109/ISQED.2006.72","DOIUrl":"https://doi.org/10.1109/ISQED.2006.72","url":null,"abstract":"Gate-length biasing is a runtime leakage reduction technique that leverages on the short-channel effect by marginally increasing the gate-length of MOS devices to significantly reduce their leakage current for a small delay penalty. The technique was shown to work effectively with multi-threshold-voltage assignment, the only mainstream approach for runtime leakage reduction. Typically, designers use threshold voltages selected by the foundries to optimize their designs. Higher threshold-voltage devices, that are less leaky but slow, are assigned to non-critical paths and lower threshold-voltage devices, that are fast but leaky, are assigned to critical paths. In this paper we study the effect of modifying threshold voltages set by the foundry on leakage reduction achieved on three large, real-world designs. We assess the impact of the availability of gate-length biasing on threshold voltage selection. We achieve comparable leakage reductions when foundry-set dual threshold voltages are used with biasing than when foundry-set triple threshold voltages are used without biasing. Our results indicate that leakage reductions can be improved if threshold voltages are carefully chosen considering the availability of gate-length biasing. We also observe that foundry-set threshold voltages are not optimal for achieving best possible leakage reductions","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126071335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Tabery, M. Craig, G. Burbach, B. Wagner, S. McGowan, P. Etter, S. Roling, C. Haidinyak, E. Ehrichs
Highly customizable and scaleable scribe-based circuits have been demonstrated as effective tools for gathering process window response curves and variations data not easily obtained through standard electrical test structure approaches or inline characterization. This work demonstrates the feasibility of using these types of circuits in design rule definition, mask validation, lithography margining, and OPC qualification and refinement. Finally, given their small form factors, they are easily adopted in high-volume manufacturing environments as process monitoring tools
{"title":"Process window and device variations evaluation using array-based characterization circuits","authors":"C. Tabery, M. Craig, G. Burbach, B. Wagner, S. McGowan, P. Etter, S. Roling, C. Haidinyak, E. Ehrichs","doi":"10.1109/ISQED.2006.107","DOIUrl":"https://doi.org/10.1109/ISQED.2006.107","url":null,"abstract":"Highly customizable and scaleable scribe-based circuits have been demonstrated as effective tools for gathering process window response curves and variations data not easily obtained through standard electrical test structure approaches or inline characterization. This work demonstrates the feasibility of using these types of circuits in design rule definition, mask validation, lithography margining, and OPC qualification and refinement. Finally, given their small form factors, they are easily adopted in high-volume manufacturing environments as process monitoring tools","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125361744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The increase in packing density has led to a higher power density in the chip which in turn has led to an increase in temperature on the chip. Temperature affects reliability, performance and power directly, motivating the need to accurately simulate the thermal profile of a chip. In literature, thermal conductivity is assumed to be a constant in order to obtain a linear system of equations which can be solved efficiently. But thermal conductivity is a nonlinear function of temperature and for silicon it varies by 22% over the range 27-80deg C (McConnell et al., 2001). If the nonlinearity of the thermal conductivity is ignored the thermal profile might be off by 10deg C. Thus to get an accurate thermal profile it is important to consider the nonlinear dependence of the thermal conductivity on temperature. In this work the nonlinear system arising out of considering the nonlinear thermal conductivity is solved efficiently using a variant of Newton-Raphson. We also study the abstraction levels under which the approximation of a periodic source by a DC source is valid
封装密度的增加导致芯片中更高的功率密度，从而导致芯片上温度的增加。温度直接影响可靠性、性能和功率，因此需要精确模拟芯片的热分布。在文献中，导热系数被假定为一个常数，以便得到一个可以有效求解的线性方程组。但导热系数是温度的非线性函数，硅的导热系数在27-80℃范围内变化22% (McConnell et al.， 2001)。如果忽略导热系数的非线性，则热廓线可能会偏离10℃。因此，为了得到准确的热廓线，考虑导热系数对温度的非线性依赖是很重要的。在本文中，由于考虑了非线性导热系数而引起的非线性系统，采用牛顿-拉夫逊的一种变体有效地求解了非线性系统。我们还研究了在哪些抽象层次下直流源对周期源的近似是有效的
{"title":"Accurate thermal analysis considering nonlinear thermal conductivity","authors":"Anand Ramalingam, D. Pan, Frank Liu, S. Nassif","doi":"10.1109/ISQED.2006.20","DOIUrl":"https://doi.org/10.1109/ISQED.2006.20","url":null,"abstract":"The increase in packing density has led to a higher power density in the chip which in turn has led to an increase in temperature on the chip. Temperature affects reliability, performance and power directly, motivating the need to accurately simulate the thermal profile of a chip. In literature, thermal conductivity is assumed to be a constant in order to obtain a linear system of equations which can be solved efficiently. But thermal conductivity is a nonlinear function of temperature and for silicon it varies by 22% over the range 27-80deg C (McConnell et al., 2001). If the nonlinearity of the thermal conductivity is ignored the thermal profile might be off by 10deg C. Thus to get an accurate thermal profile it is important to consider the nonlinear dependence of the thermal conductivity on temperature. In this work the nonlinear system arising out of considering the nonlinear thermal conductivity is solved efficiently using a variant of Newton-Raphson. We also study the abstraction levels under which the approximation of a periodic source by a DC source is valid","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123915603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the digital convergence era, new products are created at ever faster pace by combining and integrating existing and new technologies in innovative ways. Designers of these products are already facing immense productivity and quality demands. We need new architectural thinking to address the demands of the future. We need to achieve very high-level of reuse and at the same time manage the system complexity. Platformization and modularity are the key to do this. The key to true system modularity is an architectural model where the functional and physical architecture are aligned.
{"title":"Modular service-oriented platform architecture - a key enabler to SoC design quality","authors":"R. Suoranta","doi":"10.1109/ISQED.2006.89","DOIUrl":"https://doi.org/10.1109/ISQED.2006.89","url":null,"abstract":"In the digital convergence era, new products are created at ever faster pace by combining and integrating existing and new technologies in innovative ways. Designers of these products are already facing immense productivity and quality demands. We need new architectural thinking to address the demands of the future. We need to achieve very high-level of reuse and at the same time manage the system complexity. Platformization and modularity are the key to do this. The key to true system modularity is an architectural model where the functional and physical architecture are aligned.","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123472744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Statistical static timing analysis (SSTA) tools have mostly addressed the process variations of devices and lumped interconnect RC effects. This paper provides an overview of interconnect process variations of capacitive coupling and its effect on crosstalk delay and noise. The correlations among parallel plate, lateral and total capacitance is shown. Correlations between resistance and capacitance are illustrated to enable development of a simple and efficient model for delay and noise analysis. Experimental results are shown to validate the assumptions on the linearity of sensitivity of delay and noise to process variations. A methodology to account for process variations in crosstalk delay and noise is proposed
{"title":"Statistical analysis of capacitance coupling effects on delay and noise","authors":"U. Narasimha, Binu Abraham, N. Nagaraj","doi":"10.1109/ISQED.2006.121","DOIUrl":"https://doi.org/10.1109/ISQED.2006.121","url":null,"abstract":"Statistical static timing analysis (SSTA) tools have mostly addressed the process variations of devices and lumped interconnect RC effects. This paper provides an overview of interconnect process variations of capacitive coupling and its effect on crosstalk delay and noise. The correlations among parallel plate, lateral and total capacitance is shown. Correlations between resistance and capacitance are illustrated to enable development of a simple and efficient model for delay and noise analysis. Experimental results are shown to validate the assumptions on the linearity of sensitivity of delay and noise to process variations. A methodology to account for process variations in crosstalk delay and noise is proposed","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128032039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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