{"title":"An efficient method for custom integrated circuit global routing","authors":"S. Chopra, E. Rosenberg","doi":"10.1109/CICC.1988.20845","DOIUrl":null,"url":null,"abstract":"The author presents an efficient global routing technique for a custom IC. The router uses a slicing-tree floorplan representation, and wiring is assumed to lie in channels between the modules. Special features of the router are: each terminal pin of a net can be specified to be on one of the four boundaries or at the center of a module (if a boundary location is unknown); a mapping of terminal pins to module corner to reduce the graph complexity; the use of four 'imaginary modules' bounding the IC to facilitate computations using the arcs on the boundary of the IC; and options to reroute each net a specified number of times and update routing costs after any specified number of nets have been routed. The author provides a comparative study of CPU time/area/wirelength for various rerouting and cost updating strategies, in particular comparing sequential one-pass routing vs. independent (e.g. parallel) rerouting.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1988.20845","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
The author presents an efficient global routing technique for a custom IC. The router uses a slicing-tree floorplan representation, and wiring is assumed to lie in channels between the modules. Special features of the router are: each terminal pin of a net can be specified to be on one of the four boundaries or at the center of a module (if a boundary location is unknown); a mapping of terminal pins to module corner to reduce the graph complexity; the use of four 'imaginary modules' bounding the IC to facilitate computations using the arcs on the boundary of the IC; and options to reroute each net a specified number of times and update routing costs after any specified number of nets have been routed. The author provides a comparative study of CPU time/area/wirelength for various rerouting and cost updating strategies, in particular comparing sequential one-pass routing vs. independent (e.g. parallel) rerouting.<>
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