A description is given of the structure and use of the ADOPT (analog design via optimization) system. The ADOPT system consists of the circuit simulation program HSPICE (Honeywell's version of SPICE), the nonlinear optimization program SUXES-10 (licensed from Meta-Software), and an interface routine called OPTLINK to link the two programs. OPTLINK is set up to pass design parameters and simulation results between SUXES-10 and HSPICE. SUXES-10 passes the initial parameter guess vector to HSPICE. HSPICE then uses these parameters to calculate the desired circuit responses to be optimized and passes the data to SUXES, using PRINT statements. These data are compared to the desired response data and SUXES-10 determines a new set of design parameters to reduce the difference between the two responses. This process continues until SUXES-10 terminates the optimization process.<>
{"title":"ADOPT-a CAD system for analog circuit design","authors":"J. Lai, J. Kueng, H.J. Chen, F.J. Fernandez","doi":"10.1109/CICC.1988.20790","DOIUrl":"https://doi.org/10.1109/CICC.1988.20790","url":null,"abstract":"A description is given of the structure and use of the ADOPT (analog design via optimization) system. The ADOPT system consists of the circuit simulation program HSPICE (Honeywell's version of SPICE), the nonlinear optimization program SUXES-10 (licensed from Meta-Software), and an interface routine called OPTLINK to link the two programs. OPTLINK is set up to pass design parameters and simulation results between SUXES-10 and HSPICE. SUXES-10 passes the initial parameter guess vector to HSPICE. HSPICE then uses these parameters to calculate the desired circuit responses to be optimized and passes the data to SUXES, using PRINT statements. These data are compared to the desired response data and SUXES-10 determines a new set of design parameters to reduce the difference between the two responses. This process continues until SUXES-10 terminates the optimization process.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"46 48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125224005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors present a system for analog layout generation of integrated microcircuits (SALIM). The program, which combines a set of algorithms with a knowledge base, features two working modes: automatic and interactive. In the automatic mode, a knowledge-based expert system drives the algorithms. In the interactive mode, the designer task is reduced to the choice of basic elements and their association sequence.<>
{"title":"SALIM: a layout generation tool for analog ICs","authors":"M. Kayal, S. Piguet, M. Declercq, B. Hochet","doi":"10.1109/CICC.1988.20819","DOIUrl":"https://doi.org/10.1109/CICC.1988.20819","url":null,"abstract":"The authors present a system for analog layout generation of integrated microcircuits (SALIM). The program, which combines a set of algorithms with a knowledge base, features two working modes: automatic and interactive. In the automatic mode, a knowledge-based expert system drives the algorithms. In the interactive mode, the designer task is reduced to the choice of basic elements and their association sequence.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126100375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A description is given of the concept and issues of design for testability for mixed analog-digital circuits, an architecture for testable circuits of this type, general testing procedure, and the concept of analog test tables. The analog test tables contain information such as what parameters are selected for testing, what nodes need to be accessible, and testing conditions.<>
{"title":"Design for testability for mixed analog/digital ASICs","authors":"P. Fasang, D. Mullins, T. Wong","doi":"10.1109/CICC.1988.20881","DOIUrl":"https://doi.org/10.1109/CICC.1988.20881","url":null,"abstract":"A description is given of the concept and issues of design for testability for mixed analog-digital circuits, an architecture for testable circuits of this type, general testing procedure, and the concept of analog test tables. The analog test tables contain information such as what parameters are selected for testing, what nodes need to be accessible, and testing conditions.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115045299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A sigma-delta A/D (analog-to-digital) converter which achieves 81 dB of resolution and 86 dB of linearity and produces output samples at 160 kHz is described. This level of performance is about 10 dB higher than previously reported results for oversampled A/D converters in this frequency range. This device is for the ISDN U-interface. The analog part of the circuit is implemented in a 1.75- mu m 5-V CMOS process, occupies 2 mm/sup 2/ of silicon area, and consumes 75 mW of power.<>
{"title":"A 13-bit, 160 kHz sigma-delta A/D converter for ISDN","authors":"S.R. Norsworthy, I. Post","doi":"10.1109/CICC.1988.20907","DOIUrl":"https://doi.org/10.1109/CICC.1988.20907","url":null,"abstract":"A sigma-delta A/D (analog-to-digital) converter which achieves 81 dB of resolution and 86 dB of linearity and produces output samples at 160 kHz is described. This level of performance is about 10 dB higher than previously reported results for oversampled A/D converters in this frequency range. This device is for the ISDN U-interface. The analog part of the circuit is implemented in a 1.75- mu m 5-V CMOS process, occupies 2 mm/sup 2/ of silicon area, and consumes 75 mW of power.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"947 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116436106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Carlton, K. Gleason, R. Hopkins, J. Jones, K. Noonan, E. Strid
Various ideal structures such as small resistors, shorts, and transmission lines are used to verify the calibration of the measurement instrument at the probe tip. Typical measurements of package and interconnect performance are demonstrated, and sample measurements are made, including time domain reflectometry, propagation delay, isolation, and bypassing of power lines. Measurement results are shown.<>
{"title":"Accurate measurement of high-speed package and interconnect parasitics","authors":"D. Carlton, K. Gleason, R. Hopkins, J. Jones, K. Noonan, E. Strid","doi":"10.1109/CICC.1988.20920","DOIUrl":"https://doi.org/10.1109/CICC.1988.20920","url":null,"abstract":"Various ideal structures such as small resistors, shorts, and transmission lines are used to verify the calibration of the measurement instrument at the probe tip. Typical measurements of package and interconnect performance are demonstrated, and sample measurements are made, including time domain reflectometry, propagation delay, isolation, and bypassing of power lines. Measurement results are shown.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117129037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The author surveys test-related loopholes that could limit mixed signals. All the loopholes are related to one or more of three fundamental environmental characteristics. First, mixed-signal ASIC (application-specific integrated circuit) components lack the controllability and observability seen at old component/card test levels. Second, there is much closer interaction between the logic and analog portions of a design. Third, design and product life cycles are being compressed to the point where existing card and component test methodologies and processes no longer meet requirements. He shows that the key development that will lead to significant improvements in mixed signal test methodologies is the most recent generation of mixed-signal, digital signal processor (DSP)-based tester/work stations. Particularly important is computer-automated design software that these systems provide, which may establish a better environment for design-for-test and test generation development.<>
{"title":"The loophole in logic test: mixed signal ASIC","authors":"R. Prilik, J. Vanhorn, D. Leet","doi":"10.1109/CICC.1988.20880","DOIUrl":"https://doi.org/10.1109/CICC.1988.20880","url":null,"abstract":"The author surveys test-related loopholes that could limit mixed signals. All the loopholes are related to one or more of three fundamental environmental characteristics. First, mixed-signal ASIC (application-specific integrated circuit) components lack the controllability and observability seen at old component/card test levels. Second, there is much closer interaction between the logic and analog portions of a design. Third, design and product life cycles are being compressed to the point where existing card and component test methodologies and processes no longer meet requirements. He shows that the key development that will lead to significant improvements in mixed signal test methodologies is the most recent generation of mixed-signal, digital signal processor (DSP)-based tester/work stations. Particularly important is computer-automated design software that these systems provide, which may establish a better environment for design-for-test and test generation development.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123896577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A circuit has been designed and fabricated which implements a self-organizing algorithm proposed by T. Kohonen (1984). It uses a competitive learning process which modifies weights such that similar input feature vectors are clustered into distinct classes. This network learns without supervision. Matching is accomplished by computing the squared Euclidean distance at each node between the input and the current weight vector. Connections to each node are implemented with multiplying D/A converters. The weights are stored in dynamic RAM registers at each connection. The design minimizes circuit area by using unary encoding in the weight representation to permit the use of shift operations in the adaption process and by sharing the circuits used in weight adaptation and the activation computations.<>
{"title":"A self-organizing neural net chip","authors":"J. Mann, R. Lippmann, B. Berger, J. Raffel","doi":"10.1109/CICC.1988.20838","DOIUrl":"https://doi.org/10.1109/CICC.1988.20838","url":null,"abstract":"A circuit has been designed and fabricated which implements a self-organizing algorithm proposed by T. Kohonen (1984). It uses a competitive learning process which modifies weights such that similar input feature vectors are clustered into distinct classes. This network learns without supervision. Matching is accomplished by computing the squared Euclidean distance at each node between the input and the current weight vector. Connections to each node are implemented with multiplying D/A converters. The weights are stored in dynamic RAM registers at each connection. The design minimizes circuit area by using unary encoding in the weight representation to permit the use of shift operations in the adaption process and by sharing the circuits used in weight adaptation and the activation computations.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121658919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel heuristic global routing algorithm has been developed and implemented. The advantage of using heuristics for routing is that they can achieve a close-to-optimal solution in a reasonable amount of computation time. It is shown that in most cases the router achieves as good or better layout area and total wirelength as the TimberWolf global router which uses the inherently time-expensive technique of simulated annealing. It is concluded by using good heuristics that the potentially computation-intensive problem of optimal global routing can be solved efficiently without trading off a significant amount of optimality.<>
{"title":"A heuristic global router for polycell layout","authors":"V. K. De, K. Kozminski, G. Kedem","doi":"10.1109/CICC.1988.20846","DOIUrl":"https://doi.org/10.1109/CICC.1988.20846","url":null,"abstract":"A novel heuristic global routing algorithm has been developed and implemented. The advantage of using heuristics for routing is that they can achieve a close-to-optimal solution in a reasonable amount of computation time. It is shown that in most cases the router achieves as good or better layout area and total wirelength as the TimberWolf global router which uses the inherently time-expensive technique of simulated annealing. It is concluded by using good heuristics that the potentially computation-intensive problem of optimal global routing can be solved efficiently without trading off a significant amount of optimality.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114782746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A reduced circuit library using triple-level metal CMOS consisting of nine primitive logic circuits and five latch kernels is proposed for a gate array library. A grouping program has been written to combine these circuits automatically into complex functions which are then hierarchically placed and wired to achieve the density and performance of a more complex library. This approach provides a set of complex functions which is optimized for each specific application while reducing the resource needed for library development and maintenance.<>
{"title":"A reduced circuit library design system","authors":"R. Kilmoyer, D. J. Hathaway, A. Chu","doi":"10.1109/CICC.1988.20927","DOIUrl":"https://doi.org/10.1109/CICC.1988.20927","url":null,"abstract":"A reduced circuit library using triple-level metal CMOS consisting of nine primitive logic circuits and five latch kernels is proposed for a gate array library. A grouping program has been written to combine these circuits automatically into complex functions which are then hierarchically placed and wired to achieve the density and performance of a more complex library. This approach provides a set of complex functions which is optimized for each specific application while reducing the resource needed for library development and maintenance.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127745568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Trontelj, L. Trontelj, S. Ozbolt, T. Pletersek, V. Kunc
A 1.2- mu m CMOS process was developed for the design of integrated circuits requiring high digital performance combined with high analog performance. In addition, the process allows the integration of 10-V analog circuitry for telecommunication applications. Cells were designed to make use of this technology and incorporated in a test chip. Initial characterization of the ADC (analog-to-digital converter) cell ultrahigh-speed operational amplifiers and latch comparator demonstrated performance commensurate with the needs of high-speed and high-performance analog application.<>
开发了一种1.2 μ m CMOS工艺，用于设计要求高数字性能和高模拟性能相结合的集成电路。此外，该工艺还可以集成用于电信应用的10v模拟电路。细胞被设计用来利用这项技术，并被整合到一个测试芯片中。初步表征了ADC(模数转换器)单元超高速运算放大器和锁存比较器的性能与高速和高性能模拟应用的需求相称
{"title":"1.2 micron, high speed, high density CMOS analog library","authors":"J. Trontelj, L. Trontelj, S. Ozbolt, T. Pletersek, V. Kunc","doi":"10.1109/CICC.1988.20925","DOIUrl":"https://doi.org/10.1109/CICC.1988.20925","url":null,"abstract":"A 1.2- mu m CMOS process was developed for the design of integrated circuits requiring high digital performance combined with high analog performance. In addition, the process allows the integration of 10-V analog circuitry for telecommunication applications. Cells were designed to make use of this technology and incorporated in a test chip. Initial characterization of the ADC (analog-to-digital converter) cell ultrahigh-speed operational amplifiers and latch comparator demonstrated performance commensurate with the needs of high-speed and high-performance analog application.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128016233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：