{"title":"A low-power high-Q matching LNA with small-size matching calibration circuit for low power receiver","authors":"T. Ta, H. Okuni, A. Sai, M. Furuta","doi":"10.1109/RFIT.2015.7377894","DOIUrl":null,"url":null,"abstract":"To reduce power consumption of the receiver, high-Q matching low noise amplifier (LNA) can be used to reduce the power consumption of the LNA. In this work, we propose a small-size high-accuracy calibration circuit for the high-Q matching LNA. The proposed circuit is constructed by two power detectors and a comparator, which has overall area of 75×35μm2 in a 65 nm CMOS process. By comparing the amplitudes of differential input signals, the optimum setting of the matching circuit is determined. The proposed method can achieve high accuracy matching calibration without the knowledge of the input power. A LNA with proposed calibration circuit is fabricated by 65 nm CMOS process. The evaluation result proves the proposed calibration method effectiveness.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIT.2015.7377894","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
To reduce power consumption of the receiver, high-Q matching low noise amplifier (LNA) can be used to reduce the power consumption of the LNA. In this work, we propose a small-size high-accuracy calibration circuit for the high-Q matching LNA. The proposed circuit is constructed by two power detectors and a comparator, which has overall area of 75×35μm2 in a 65 nm CMOS process. By comparing the amplitudes of differential input signals, the optimum setting of the matching circuit is determined. The proposed method can achieve high accuracy matching calibration without the knowledge of the input power. A LNA with proposed calibration circuit is fabricated by 65 nm CMOS process. The evaluation result proves the proposed calibration method effectiveness.