Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377895
Zongming Duan, Xiaolan Tang, Q. Ma, Yuefei Dai, F. Lin
A 1-4GHz receive front-end is implemented in 0.18 μm CMOS technology for digital array radar applications. The front-end consists of broadband balun-LNA, down-conversion mixer, voltage gain control amplifier (VGA), differential-to-single driver (D-S Driver), LO driver and on chip temperature self-adaptive gain control circuit. The front-end achieves a gain range of 5-25 dB, a noise figure of 8.5dB, and an output P-1dB of 5.2 dBm. The gain difference is less than 1.2 dB within -55 ~ +85°C operating temperature across 1-4 GHz. The total power consumption is 150 mW, and the die area is 1.2 mm2 including pads.
{"title":"A 1–4GHz CM OS receive front-end for digital array radars","authors":"Zongming Duan, Xiaolan Tang, Q. Ma, Yuefei Dai, F. Lin","doi":"10.1109/RFIT.2015.7377895","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377895","url":null,"abstract":"A 1-4GHz receive front-end is implemented in 0.18 μm CMOS technology for digital array radar applications. The front-end consists of broadband balun-LNA, down-conversion mixer, voltage gain control amplifier (VGA), differential-to-single driver (D-S Driver), LO driver and on chip temperature self-adaptive gain control circuit. The front-end achieves a gain range of 5-25 dB, a noise figure of 8.5dB, and an output P-1dB of 5.2 dBm. The gain difference is less than 1.2 dB within -55 ~ +85°C operating temperature across 1-4 GHz. The total power consumption is 150 mW, and the die area is 1.2 mm2 including pads.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124969621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377897
S. Amakawa, K. Katayama, K. Takano, T. Yoshida, M. Fujishima
Formal comparative analysis is presented of three known de-embedding and characteristic impedance estimation techniques for on-chip transmission lines, used after probe-tip calibration. Somewhat counterintuitively, experience accumulated in the field seems to suggest that the apparently most simplistic of the three gives much better results than the other two, more "accurate-looking" techniques. The reason, however, never seems to have been explained clearly. This paper attempts to explain why and suggests some new alternative techniques.
{"title":"Comparative analysis of on-chip transmission line de-embedding techniques","authors":"S. Amakawa, K. Katayama, K. Takano, T. Yoshida, M. Fujishima","doi":"10.1109/RFIT.2015.7377897","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377897","url":null,"abstract":"Formal comparative analysis is presented of three known de-embedding and characteristic impedance estimation techniques for on-chip transmission lines, used after probe-tip calibration. Somewhat counterintuitively, experience accumulated in the field seems to suggest that the apparently most simplistic of the three gives much better results than the other two, more \"accurate-looking\" techniques. The reason, however, never seems to have been explained clearly. This paper attempts to explain why and suggests some new alternative techniques.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116013938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377890
Chong-Yi Liou, Chi-Jung Kuo, Si-Sheng Lin, Shau-Gang Mao
This study presents the metamaterial-like printed spiral coils (PSCs) for improving the proximity effect of metal plates in wireless power transmission. The proposed four-PSC system is experimentally and theoretically verified by power transmission, impedance matching, resonant frequency, magnetic field distribution, and induced eddy current on metal plate. Results demonstrate that the transmission of the four-PSC system is 9.2 dB higher than the conventional two-PSC system when the backside metal plates are added.
{"title":"Printed spiral metamaterial resonators for wireless powering system with proximal metal plates","authors":"Chong-Yi Liou, Chi-Jung Kuo, Si-Sheng Lin, Shau-Gang Mao","doi":"10.1109/RFIT.2015.7377890","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377890","url":null,"abstract":"This study presents the metamaterial-like printed spiral coils (PSCs) for improving the proximity effect of metal plates in wireless power transmission. The proposed four-PSC system is experimentally and theoretically verified by power transmission, impedance matching, resonant frequency, magnetic field distribution, and induced eddy current on metal plate. Results demonstrate that the transmission of the four-PSC system is 9.2 dB higher than the conventional two-PSC system when the backside metal plates are added.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116052059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377940
Shu Yang, Sheng-gen Liu, Cheng Liu, Yunyou Lu, K. J. Chen
Effective interface engineering technology in GaN-based insulated-gate heteroj unction transistors are of critical significance to enhance device stability and suppress current collapse. In this paper, we present an interface engineering approach featuring in situ low-damage remote plasma treatment prior to the dielectric deposition, to realize high-performance and high-stability GaN-based metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs). This technology can remove the native oxide while forming a monocrystal-like nitridation interfacial-layer (NIL) on the GaN surface. The Al2O3(NIL)/GaN/AlGaN/GaN MIS heterostructures with high-quality interface exhibit well-behaved electrical characteristics, including suppressed gate leakage current, a steep subthreshold swing of ~64 mV/dec, a small hysteresis of ~0.09 V, tiny frequency/temperature-dispersions in the capacitance-voltage characteristics, and low interface trap density of ~6×1011 - 6×1012 cm-2eV-1.
{"title":"Nitridation interfacial-layer technology for enhanced stability in GaN-based power devices","authors":"Shu Yang, Sheng-gen Liu, Cheng Liu, Yunyou Lu, K. J. Chen","doi":"10.1109/RFIT.2015.7377940","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377940","url":null,"abstract":"Effective interface engineering technology in GaN-based insulated-gate heteroj unction transistors are of critical significance to enhance device stability and suppress current collapse. In this paper, we present an interface engineering approach featuring in situ low-damage remote plasma treatment prior to the dielectric deposition, to realize high-performance and high-stability GaN-based metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs). This technology can remove the native oxide while forming a monocrystal-like nitridation interfacial-layer (NIL) on the GaN surface. The Al2O3(NIL)/GaN/AlGaN/GaN MIS heterostructures with high-quality interface exhibit well-behaved electrical characteristics, including suppressed gate leakage current, a steep subthreshold swing of ~64 mV/dec, a small hysteresis of ~0.09 V, tiny frequency/temperature-dispersions in the capacitance-voltage characteristics, and low interface trap density of ~6×1011 - 6×1012 cm-2eV-1.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131057966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377941
F. Lin, Weiqiang Qian, Lei Li, Mehdi Khan
This paper will present the recent development of large-signal modeling cum PA design based on Dynax GaN HEMT devices. A modified Angelov model is used to model the pulse I-V data. Improved modeling results to address the trapping effect will be given together with new model parameter extraction methodology. The model is implemented in a commercial EDA tools for PA design simulation.
本文将介绍基于Dynax GaN HEMT器件的大信号建模和PA设计的最新进展。采用改进的Angelov模型对脉冲I-V数据进行建模。将给出改进的模型结果，以解决捕获效应，并给出新的模型参数提取方法。该模型在商用EDA工具中实现，用于PA设计仿真。
{"title":"Large-signal modeling of GaN devices with emphasis on trapping effect and thermal challenges (Invited)","authors":"F. Lin, Weiqiang Qian, Lei Li, Mehdi Khan","doi":"10.1109/RFIT.2015.7377941","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377941","url":null,"abstract":"This paper will present the recent development of large-signal modeling cum PA design based on Dynax GaN HEMT devices. A modified Angelov model is used to model the pulse I-V data. Improved modeling results to address the trapping effect will be given together with new model parameter extraction methodology. The model is implemented in a commercial EDA tools for PA design simulation.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"316 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131644266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377926
Congbing Li, Haruo Kobayashi
A glitch-free time-to-digital converter (TDC) based on Gray code is presented. This architecture can reduce hardware, power consumption, as well as chip area significantly compared to a flash type TDC, while keeping comparable performance and glitch-free characteristics. Its proof-of-concept prototype was implemented on FPGA, and the measurement and simulation results validate the effectiveness of the proposed architecture.
{"title":"A gray code based time-to-digital converter architecture and its FPGA implementation","authors":"Congbing Li, Haruo Kobayashi","doi":"10.1109/RFIT.2015.7377926","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377926","url":null,"abstract":"A glitch-free time-to-digital converter (TDC) based on Gray code is presented. This architecture can reduce hardware, power consumption, as well as chip area significantly compared to a flash type TDC, while keeping comparable performance and glitch-free characteristics. Its proof-of-concept prototype was implemented on FPGA, and the measurement and simulation results validate the effectiveness of the proposed architecture.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123475911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377936
Takaho Sekiguchi, Y. Okano, Naoki Ohmura, S. Ogino
In case of payment system with NFC (Near Field Communication)/HF-RFID (Radio Frequency IDentification) installed into the smart-phone, NFC antenna's communication performance at 13.56MHz is deteriorated by the battery case or circuit boards. To solve this problem, the magnetic sheet with high permeability is inserted into the NFC/HF-RFID antenna and metal object. Thin magnetic compound or sintered ferrite has been used as the high permeability sheet. However, these sheet thickness could not be suppressed to improve the NFC/HF-RFID antenna's performance. In order to make thickness of these materials thinner, we propose amorphous magnetic sheet. Besides because the loss of amorphous magnetic sheet is large, that loss suppression technique is also proposed.
{"title":"Study on effective pattern of magnetic sheet attached on NFC antenna","authors":"Takaho Sekiguchi, Y. Okano, Naoki Ohmura, S. Ogino","doi":"10.1109/RFIT.2015.7377936","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377936","url":null,"abstract":"In case of payment system with NFC (Near Field Communication)/HF-RFID (Radio Frequency IDentification) installed into the smart-phone, NFC antenna's communication performance at 13.56MHz is deteriorated by the battery case or circuit boards. To solve this problem, the magnetic sheet with high permeability is inserted into the NFC/HF-RFID antenna and metal object. Thin magnetic compound or sintered ferrite has been used as the high permeability sheet. However, these sheet thickness could not be suppressed to improve the NFC/HF-RFID antenna's performance. In order to make thickness of these materials thinner, we propose amorphous magnetic sheet. Besides because the loss of amorphous magnetic sheet is large, that loss suppression technique is also proposed.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124031481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377910
Di Li, Lei Zhang, Yan Wang
This paper proposes a 60-GHz two stage low-noise amplifier (LNA) and a three stage power amplifier (PA) designed with over neutralization and optimized inter-stage matching techniques in 65nm CMOS process. Thanks to the gain-boosting from over neutralization techniques and insertion loss reduction with bandwidth extension from proposed inter-stage matching technique based on micro-strip lines and transformers, the LNA achieves a 18dB gain, 7GHz 3-dB bandwidth, 2.1dBm ZW with a noise figure of 4.9dB, while consuming only 20mW from a supply of 1.2V. And the PA features 20dB gain, >8GHz bandwidth, a 10.4dBm Z1dB with 14% PAE and 14dBm Psat. The proposed techniques also help to reduce the die sizes of the LNA and PA are reduced to 1.18*0.51mm2 and 1.17*0.47mm2 as well.
{"title":"Design of 60-GHz amplifiers based on over neutralization and optimized inter-stage matching networks in 65-nm CMOS","authors":"Di Li, Lei Zhang, Yan Wang","doi":"10.1109/RFIT.2015.7377910","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377910","url":null,"abstract":"This paper proposes a 60-GHz two stage low-noise amplifier (LNA) and a three stage power amplifier (PA) designed with over neutralization and optimized inter-stage matching techniques in 65nm CMOS process. Thanks to the gain-boosting from over neutralization techniques and insertion loss reduction with bandwidth extension from proposed inter-stage matching technique based on micro-strip lines and transformers, the LNA achieves a 18dB gain, 7GHz 3-dB bandwidth, 2.1dBm ZW with a noise figure of 4.9dB, while consuming only 20mW from a supply of 1.2V. And the PA features 20dB gain, >8GHz bandwidth, a 10.4dBm Z1dB with 14% PAE and 14dBm Psat. The proposed techniques also help to reduce the die sizes of the LNA and PA are reduced to 1.18*0.51mm2 and 1.17*0.47mm2 as well.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125472861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents an embedded antenna design for wireless sensor modules for application in advanced greenhouses. The wireless sensor modules are realized based on the UHF RFID tag plus low-power MCU chip [1]. In the antenna design, resonator models are used to tailor the input impedance of the antenna to satisfy the condition of complex conjugate matching, and hence the maximum power transfer between the RFID tag chip and the antenna. The proposed embedded antenna possesses an open-ended quarter wavelength strip monopole to generate a zero resonance, lowering the real part of the input impedance of the antenna, and a parallel chip capacitor near the feeding terminal to provide a pole resonance, pulling up the imaginary part of the impedance, to achieve conjugate matching to the highly capacitive RFID tag chip, whose input impedance is 18 - j171 Ω. The simulated realized gain of the antenna is -0.26 dBi, and the associated maximum read range is 8 m based on Friis' equation with the maximum EIRP of 4 W.
{"title":"Embedded antenna design based on zero and pole resonances for wireless sensor modules for applications in advanced greenhouses","authors":"Chun-Chih Liu, Shih-An Yang, Tzu-Heng Cheng, Shih-Yuan Chen","doi":"10.1109/RFIT.2015.7377935","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377935","url":null,"abstract":"This paper presents an embedded antenna design for wireless sensor modules for application in advanced greenhouses. The wireless sensor modules are realized based on the UHF RFID tag plus low-power MCU chip [1]. In the antenna design, resonator models are used to tailor the input impedance of the antenna to satisfy the condition of complex conjugate matching, and hence the maximum power transfer between the RFID tag chip and the antenna. The proposed embedded antenna possesses an open-ended quarter wavelength strip monopole to generate a zero resonance, lowering the real part of the input impedance of the antenna, and a parallel chip capacitor near the feeding terminal to provide a pole resonance, pulling up the imaginary part of the impedance, to achieve conjugate matching to the highly capacitive RFID tag chip, whose input impedance is 18 - j171 Ω. The simulated realized gain of the antenna is -0.26 dBi, and the associated maximum read range is 8 m based on Friis' equation with the maximum EIRP of 4 W.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123228177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377928
Yen-Liang Yeh, Yu-Cheng Liu, Hong-Yeh Chang, Kevin Chen
In this paper, a D-band divider-by-3 injection-locked frequency divider is presented using 65 CMOS process. By using the technique of the second harmonic boosting, the input sensitivity and locking range can be enhanced in the millimeter-wave band without additional dc power consumption. As the input frequency is 134.6 GHz with a RF power of -8.5 dBm, the measured locking range is 0.4 GHz without varactor tuning, and the output power is high than -18 dBm. The core dc power consumption is 2.3 mW.
{"title":"Evaluation of a D-band divide-by-3 injection-locked frequency divider in 65 nm CMOS process","authors":"Yen-Liang Yeh, Yu-Cheng Liu, Hong-Yeh Chang, Kevin Chen","doi":"10.1109/RFIT.2015.7377928","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377928","url":null,"abstract":"In this paper, a D-band divider-by-3 injection-locked frequency divider is presented using 65 CMOS process. By using the technique of the second harmonic boosting, the input sensitivity and locking range can be enhanced in the millimeter-wave band without additional dc power consumption. As the input frequency is 134.6 GHz with a RF power of -8.5 dBm, the measured locking range is 0.4 GHz without varactor tuning, and the output power is high than -18 dBm. The core dc power consumption is 2.3 mW.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121813394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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