A linear-in-dB analog baseband circuit for low power 60GHz receiver in standard 65nm CMOS

Yanjie Wang, C. Hull, Glenn Murata, S. Ravid
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引用次数: 21

Abstract

This paper presents an analog baseband (ABB) circuit for low power 60 GHz wireless receiver in standard 65 nm CMOS. The proposed analog baseband system combines variable gain amplifiers (VGA) with a 3rd-order type II Chebyshev filter and provides linear steps as well as filter tuning range to achieve sufficient out-of-band rejection. The ABB demonstrates 2 dB gain step tuning range from 3 - 31 dB, 3-dB bandwidth of 980 MHz, OP1dB of 0dBm, and noise figure of 6 dB to 21 dB. The ABB consumes 48 mW at max gain setting and 32 mW at minimum gain setting from a 1.1 V supply. The entire ABB occupies an area of 1.1 mm2 with active area of 0.2 mm2.
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一种用于标准65nm CMOS低功耗60GHz接收机的db级线性模拟基带电路
本文提出了一种用于低功耗60ghz无线接收机的标准65nm CMOS模拟基带电路。所提出的模拟基带系统将可变增益放大器(VGA)与三阶II型切比雪夫滤波器相结合,并提供线性步进和滤波器调谐范围,以实现足够的带外抑制。ABB演示了2 dB增益步进调谐范围为3- 31 dB, 3 dB带宽为980 MHz, OP1dB为0dBm,噪声系数为6 dB至21 dB。ABB在1.1 V电源的最大增益设置下消耗48兆瓦,在最小增益设置下消耗32兆瓦。整个ABB占地面积1.1 mm2,活动面积0.2 mm2。
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