Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569607
B. Ku, O. Inac, Michael Chang, Gabriel M. Rebeiz
This paper presents the first simultaneous 8-transmit and 8-receive paths 75-85 GHz phased array RFIC for FMCW automotive radars. The receive path has two separate I/Q mixers each connected to 4-element phased arrays for RF and digital beamforming. The chip also contains a build-in-self-test system (BIST) for the transmit and receive paths. Measurements on a flip-chip prototype show a gain >24 dB at 77 GHz, -25 dB coupling between adjacent channels in the transmit and receive paths (<;-45 dB between non-adjacent channels), and <;-50 dB coupling between the transmit and receive portions of the chip.
{"title":"75–85 GHz flip-chip phased array RFIC with simultaneous 8-transmit and 8-receive paths for automotive radar applications","authors":"B. Ku, O. Inac, Michael Chang, Gabriel M. Rebeiz","doi":"10.1109/RFIC.2013.6569607","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569607","url":null,"abstract":"This paper presents the first simultaneous 8-transmit and 8-receive paths 75-85 GHz phased array RFIC for FMCW automotive radars. The receive path has two separate I/Q mixers each connected to 4-element phased arrays for RF and digital beamforming. The chip also contains a build-in-self-test system (BIST) for the transmit and receive paths. Measurements on a flip-chip prototype show a gain >24 dB at 77 GHz, -25 dB coupling between adjacent channels in the transmit and receive paths (<;-45 dB between non-adjacent channels), and <;-50 dB coupling between the transmit and receive portions of the chip.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125241775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569594
Iman Madadi, Massoud Tohidian, R. Staszewski
We propose a highly reconfigurable superheterodyne receiver that employs a 3rd-order complex IQ charge-sharing band-pass filter (BPF) for image rejection and 1st-order feedback based RF-BPF for channel selection filtering. The operating RF input frequency of the receiver is 500 MHz-1.2 GHz with varying high-IF range of 33-80 MHz. All the gain stages are merely inverter-based gm stages. The total gain of the receiver is 35dB and in-band IIP3 at midgain is +10 dBm. The NF of the receiver is 6.7dB, which is acceptable for the receiver without an LNA. The architecture is highly reconfigurable and follows the technology scaling. The RX occupies 0.47 mm2 of active area and consumes 24.5 mA at 1.2V power supply.
{"title":"A 65nm CMOS high-IF superheterodyne receiver with a High-Q complex BPF","authors":"Iman Madadi, Massoud Tohidian, R. Staszewski","doi":"10.1109/RFIC.2013.6569594","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569594","url":null,"abstract":"We propose a highly reconfigurable superheterodyne receiver that employs a 3rd-order complex IQ charge-sharing band-pass filter (BPF) for image rejection and 1st-order feedback based RF-BPF for channel selection filtering. The operating RF input frequency of the receiver is 500 MHz-1.2 GHz with varying high-IF range of 33-80 MHz. All the gain stages are merely inverter-based gm stages. The total gain of the receiver is 35dB and in-band IIP3 at midgain is +10 dBm. The NF of the receiver is 6.7dB, which is acceptable for the receiver without an LNA. The architecture is highly reconfigurable and follows the technology scaling. The RX occupies 0.47 mm2 of active area and consumes 24.5 mA at 1.2V power supply.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126713043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569531
Lixue Kuang, B. Chi, Haikun Jia, Zuochang Ye, Wen Jia, Zhihua Wang
Summary form only given. Co-design of 60GHz wideband front-end IC with on-chip Tx/Rx switch in 65nm CMOS is presented. Passive macro-modeling (pmm) is utilized to convert S-parameter files from passive component EM simulations to state-space models in circuit netlist format which could be used in commercial SPICE simulator for various analyses without convergence issues. The co-design of on-chip switch and LNA/PA could achieve wideband matching and reduce the effects of insertion loss of on-chip Tx/Rx switch. Combining with gain boosting technique in LNA design and lumped-component based design methodology, the implemented 60GHz front-end IC with on-chip Tx/Rx switch achieves 3dB gain bandwidth of 12GHz with maximum gain 17.8dB and minimum NF 5.6dB in Rx mode and 3dB gain bandwidth of 10GHz with saturated output power 5.6dBm in Tx mode, and only consumes 1.0mm×1.2mm die area (including pads).
{"title":"Co-design of 60GHz wideband front-end IC with on-chip Tx/Rx switch based on passive macro-modeling","authors":"Lixue Kuang, B. Chi, Haikun Jia, Zuochang Ye, Wen Jia, Zhihua Wang","doi":"10.1109/RFIC.2013.6569531","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569531","url":null,"abstract":"Summary form only given. Co-design of 60GHz wideband front-end IC with on-chip Tx/Rx switch in 65nm CMOS is presented. Passive macro-modeling (pmm) is utilized to convert S-parameter files from passive component EM simulations to state-space models in circuit netlist format which could be used in commercial SPICE simulator for various analyses without convergence issues. The co-design of on-chip switch and LNA/PA could achieve wideband matching and reduce the effects of insertion loss of on-chip Tx/Rx switch. Combining with gain boosting technique in LNA design and lumped-component based design methodology, the implemented 60GHz front-end IC with on-chip Tx/Rx switch achieves 3dB gain bandwidth of 12GHz with maximum gain 17.8dB and minimum NF 5.6dB in Rx mode and 3dB gain bandwidth of 10GHz with saturated output power 5.6dBm in Tx mode, and only consumes 1.0mm×1.2mm die area (including pads).","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116159859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569564
A. Visweswaran, J. Long, L. Galatro, M. Spirito, R. Staszewski
An FM demodulator operating across 8GHz IF bandwidth for application in low-power, wideband heterodyne receivers is presented. A 4-stage ring oscillator is frequency modulated by a wideband input. Locking to 1/4th the input frequency, it divides the FM deviation by four, thereby reducing the energy required for wideband demodulation to 0.75nJ/bit. Autocorrelation of the quadrature-phased outputs using a new low-power folded CMOS mixer is capable of detecting FM up to 400Mb/s over 2-10GHz IF. The inductorless 65nm CMOS prototype circuit occupies 0.17mm2 and dissipates 3mW from 1.2V.
{"title":"An FM demodulator operating across 2–10GHz IF","authors":"A. Visweswaran, J. Long, L. Galatro, M. Spirito, R. Staszewski","doi":"10.1109/RFIC.2013.6569564","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569564","url":null,"abstract":"An FM demodulator operating across 8GHz IF bandwidth for application in low-power, wideband heterodyne receivers is presented. A 4-stage ring oscillator is frequency modulated by a wideband input. Locking to 1/4th the input frequency, it divides the FM deviation by four, thereby reducing the energy required for wideband demodulation to 0.75nJ/bit. Autocorrelation of the quadrature-phased outputs using a new low-power folded CMOS mixer is capable of detecting FM up to 400Mb/s over 2-10GHz IF. The inductorless 65nm CMOS prototype circuit occupies 0.17mm2 and dissipates 3mW from 1.2V.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122443293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569514
K. Sankaragomathi, L. Callaghan, R. Ruby, B. Otis
We present a technique to reduce the close-in phase noise of high-Q (FBAR/MEMS/crystal) oscillators. The proposed technique suppresses the up-conversion of 1/f noise via AM-PM conversion by the addition of a non-linear capacitor to the tank. The proposed AM-PM suppression technique has no additional power penalty and incurs a minimal area penalty. Measurements from multiple dies of a 1.9GHZ FBAR oscillator show ≥3.5dB reduction in close-in phase noise using the proposed technique. The FBAR oscillator achieves a measured phase noise of -88dBc/Hz @ 1kHz, -116dBc/Hz @ 10kHz, -146dBc/Hz @ 1MHz offsets. The oscillator with the proposed technique achieves a Figure of Merit (FOM) of 220dB, which is 5.5dB better than the FBAR oscillator with lowest close-in phase noise reported to date [1].
{"title":"A 220dB FOM, 1.9GHz oscillator using a phase noise reduction technique for high-Q oscillators","authors":"K. Sankaragomathi, L. Callaghan, R. Ruby, B. Otis","doi":"10.1109/RFIC.2013.6569514","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569514","url":null,"abstract":"We present a technique to reduce the close-in phase noise of high-Q (FBAR/MEMS/crystal) oscillators. The proposed technique suppresses the up-conversion of 1/f noise via AM-PM conversion by the addition of a non-linear capacitor to the tank. The proposed AM-PM suppression technique has no additional power penalty and incurs a minimal area penalty. Measurements from multiple dies of a 1.9GHZ FBAR oscillator show ≥3.5dB reduction in close-in phase noise using the proposed technique. The FBAR oscillator achieves a measured phase noise of -88dBc/Hz @ 1kHz, -116dBc/Hz @ 10kHz, -146dBc/Hz @ 1MHz offsets. The oscillator with the proposed technique achieves a Figure of Merit (FOM) of 220dB, which is 5.5dB better than the FBAR oscillator with lowest close-in phase noise reported to date [1].","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129104788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569556
M. Mehrpoo, R. Staszewski
To achieve ultimately flexible multi-core radio operation, wide-band receiver RF front-ends must be robust against interference well in excess of the requirements usually specified by a radio standard. In this paper, a highly selective, very linear low-noise transconductance amplifier (LNTA) capable of large-signal handling for current-mode receiver (RX) front-ends is proposed and implemented in 65-nm CMOS. It is shown that by combining on-chip highQ bandpass filters with a push/pull class-AB common-gate stage, a measured 1-dB desensitization point (B1dB) and large-signal IIP3 of +8 dBm and +20 dBm, respectively, can be achieved. In addition, by applying a noise cancellation technique, via an auxiliary push/pull class-AB common-source stage, the proposed LNTA measures a moderate NF of 5.9 dB, which is a very competitive number for such high value of B1dB. The circuit consumes 7.5 mA at 1.5 V.
{"title":"A highly selective LNTA capable of large-signal handling for RF receiver front-ends","authors":"M. Mehrpoo, R. Staszewski","doi":"10.1109/RFIC.2013.6569556","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569556","url":null,"abstract":"To achieve ultimately flexible multi-core radio operation, wide-band receiver RF front-ends must be robust against interference well in excess of the requirements usually specified by a radio standard. In this paper, a highly selective, very linear low-noise transconductance amplifier (LNTA) capable of large-signal handling for current-mode receiver (RX) front-ends is proposed and implemented in 65-nm CMOS. It is shown that by combining on-chip highQ bandpass filters with a push/pull class-AB common-gate stage, a measured 1-dB desensitization point (B1dB) and large-signal IIP3 of +8 dBm and +20 dBm, respectively, can be achieved. In addition, by applying a noise cancellation technique, via an auxiliary push/pull class-AB common-source stage, the proposed LNTA measures a moderate NF of 5.9 dB, which is a very competitive number for such high value of B1dB. The circuit consumes 7.5 mA at 1.5 V.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114615227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569572
Massoud Tohidian, Seyed Amir Reza Ahmadi Mehr, R. Bogdan
We propose an ultra-low phase noise oscillator topology that works on the premise that coupling a second identical oscillator core would reduce the overall phase noise by 3 dB. For each core, a high-swing class-C oscillator is used to achieve the lowest phase noise. The realized oscillator is tunable from 4.07-4.91 GHz, drawing 39-59 mA from a 2.15 V power supply. The measured phase noise is -146.7 dBc/Hz and -163.1 dBc/Hz at 3 MHz and 20 MHz offset, respectively, from 4.07 GHz carrier. This is the lowest ever reported phase noise in bulk CMOS IC. This phase noise meets GSM900 normal basestation receiver and mobile station transmitter standards, which have the toughest phase noise requirements in cellular communications.
{"title":"Dual-core high-swing class-C oscillator with ultra-low phase noise","authors":"Massoud Tohidian, Seyed Amir Reza Ahmadi Mehr, R. Bogdan","doi":"10.1109/RFIC.2013.6569572","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569572","url":null,"abstract":"We propose an ultra-low phase noise oscillator topology that works on the premise that coupling a second identical oscillator core would reduce the overall phase noise by 3 dB. For each core, a high-swing class-C oscillator is used to achieve the lowest phase noise. The realized oscillator is tunable from 4.07-4.91 GHz, drawing 39-59 mA from a 2.15 V power supply. The measured phase noise is -146.7 dBc/Hz and -163.1 dBc/Hz at 3 MHz and 20 MHz offset, respectively, from 4.07 GHz carrier. This is the lowest ever reported phase noise in bulk CMOS IC. This phase noise meets GSM900 normal basestation receiver and mobile station transmitter standards, which have the toughest phase noise requirements in cellular communications.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126228651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569555
Jaeyoung Lee, Jeiyoung Lee, Bonkee Kim, Boeun Kim, C. Nguyen
A wideband linearization technique using tunable multiple gated transistors (MGTRs) is proposed. Extra tunable input capacitors and the modified derivative superposition (DS) method are also adopted to increase the amplifier's linearity at RF. A low-noise amplifier (LNA) employing the proposed linearization technique has been developed with 0.18-μm CMOS process for various mobile TV standards in UHF band (470-862 MHz). The LNA achieves 19-dBm IIP3, 16.5-dB gain, and 1.33-dB NF with 10.8-mW power consumption. Over the desired UHF band, the LNA increases the average IIP3 obtained with off-state auxiliary transistor by 11.7 dBm.
{"title":"A highly linear low-noise amplifier using a wideband linearization technique with tunable multiple gated transistors","authors":"Jaeyoung Lee, Jeiyoung Lee, Bonkee Kim, Boeun Kim, C. Nguyen","doi":"10.1109/RFIC.2013.6569555","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569555","url":null,"abstract":"A wideband linearization technique using tunable multiple gated transistors (MGTRs) is proposed. Extra tunable input capacitors and the modified derivative superposition (DS) method are also adopted to increase the amplifier's linearity at RF. A low-noise amplifier (LNA) employing the proposed linearization technique has been developed with 0.18-μm CMOS process for various mobile TV standards in UHF band (470-862 MHz). The LNA achieves 19-dBm IIP3, 16.5-dB gain, and 1.33-dB NF with 10.8-mW power consumption. Over the desired UHF band, the LNA increases the average IIP3 obtained with off-state auxiliary transistor by 11.7 dBm.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126513742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569593
M. Kitsunezuka, K. Kunihiro
A low-power, wideband CMOS receiver for spectrum-sensing cognitive radio sensor networks is presented. The low-IF receiver equipped with an inverter-based LNA-balun and I/Q sub-threshold rectifier enables low-power and high-speed spectrum sensing. For further extension to support higher data-rate radio systems, our local oscillator provides a frequency-dividing function when a low-phase-noise signal source is optionally used. A prototype chip fabricated in a 65-nm CMOS process can support a wide frequency range of 0.2-2.5 GHz with 43-dB maximum gain, 6-dB NF, and -9-dBm IIP3 and only occupies 0.6 mm2 while consuming as low as 5-9 mW at a 0.6-V supply.
{"title":"A 5–9-mw, 0.2–2.5-GHz CMOS low-if receiver for spectrum-sensing cognitive radio sensor networks","authors":"M. Kitsunezuka, K. Kunihiro","doi":"10.1109/RFIC.2013.6569593","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569593","url":null,"abstract":"A low-power, wideband CMOS receiver for spectrum-sensing cognitive radio sensor networks is presented. The low-IF receiver equipped with an inverter-based LNA-balun and I/Q sub-threshold rectifier enables low-power and high-speed spectrum sensing. For further extension to support higher data-rate radio systems, our local oscillator provides a frequency-dividing function when a low-phase-noise signal source is optionally used. A prototype chip fabricated in a 65-nm CMOS process can support a wide frequency range of 0.2-2.5 GHz with 43-dB maximum gain, 6-dB NF, and -9-dBm IIP3 and only occupies 0.6 mm2 while consuming as low as 5-9 mW at a 0.6-V supply.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128152057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569613
L. Leyssenne, S. Wane, D. Bajon, P. Descamps, Rosine Coq-Germanicus
This paper proposes an analysis and modeling of a reconfigurable sensor for the non-destructive remote extraction and monitoring of dielectric material and liquid properties, towards substance identification or distribution cartography.
{"title":"Reconfigurable sensors for extraction of dielectric material and liquid properties","authors":"L. Leyssenne, S. Wane, D. Bajon, P. Descamps, Rosine Coq-Germanicus","doi":"10.1109/RFIC.2013.6569613","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569613","url":null,"abstract":"This paper proposes an analysis and modeling of a reconfigurable sensor for the non-destructive remote extraction and monitoring of dielectric material and liquid properties, towards substance identification or distribution cartography.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130214080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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